linux-toradex.git/include/asm-mips/cpu.h, branch v2.6.27.31 Linux kernel for Apalis and Colibri modules [MIPS] modify the MIPS CPU classfication 2008-07-15T17:44:28+00:00 Chen, Huacai huacai.chen@intel.com 2008-06-10T01:05:08+00:00 2954c02a884dc0ba9e91882c0aba13bcb9d22e6c Signed-off-by: Huacai Chen <huacai.chen@intel.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
Signed-off-by: Huacai Chen <huacai.chen@intel.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
[MIPS] Move arch/mips/philips to arch/mips/nxp 2008-04-28T16:14:26+00:00 Daniel Laird daniel.j.laird@nxp.com 2008-03-06T09:07:18+00:00 a92b05880d261e9017ef8e7d5b6b01e0e5aa991d Signed-off-by: daniel.j.laird <daniel.j.laird@nxp.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
Signed-off-by: daniel.j.laird <daniel.j.laird@nxp.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
[MIPS] Add support for MIPS CMP platform. 2008-04-28T16:14:26+00:00 Ralf Baechle ralf@linux-mips.org 2008-04-28T16:14:26+00:00 39b8d5254246ac56342b72f812255c8f7a74dca9 Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
[MIPS] Alchemy: Au1210/Au1250 CPU support 2008-01-29T10:14:59+00:00 Manuel Lauss mano@roarinelk.homelinux.net 2007-12-06T08:07:55+00:00 237cfee1db66147aef4457f02b56a41e6f84bfd3 This patch adds IDs for new Au1200 variants: Au1210 and Au1250. They are essentially identical to the Au1200 except for the Au1210 which has a different SoC-ID in the PRId register [bits 31:24]. The Au1250 is a "Au1200 V0.2". Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
This patch adds IDs for new Au1200 variants: Au1210 and Au1250.
They are essentially identical to the Au1200 except for the Au1210
which has a different SoC-ID in the PRId register [bits 31:24].
The Au1250 is a "Au1200 V0.2".

Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
[MIPS] Convert list of CPU types from #define to enum. 2007-10-11T22:46:16+00:00 Ralf Baechle ralf@linux-mips.org 2007-10-11T22:46:16+00:00 36cfbaad815908f54872a7b471e9a7a09b4084a4 Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
[MIPS] Sibyte: Replace SB1 cachecode with standard R4000 class cache code. 2007-10-11T22:46:05+00:00 Ralf Baechle ralf@linux-mips.org 2007-10-11T22:46:05+00:00 641e97f318870921d048154af6807e46e43c307a It may not be perfect yet but the SB1 code is badly borken and has horrible performance issues. Downside: This seriously breaks support for pass 1 parts of the BCM1250 where indexed cacheops don't work quite reliable but I seem to be the last one on the planet with a pass 1 part anyway. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
It may not be perfect yet but the SB1 code is badly borken and has
horrible performance issues.

Downside: This seriously breaks support for pass 1 parts of the BCM1250
where indexed cacheops don't work quite reliable but I seem to be the
last one on the planet with a pass 1 part anyway.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
[MIPS] Add support for BCM47XX CPUs. 2007-10-11T22:46:02+00:00 Aurelien Jarno aurelien@aurel32.net 2007-09-25T13:40:12+00:00 1c0c13eb935c95fd2ca0b0aca6dd4860487fb242 Note that the BCM4710 does not support the wait instruction, this is not a mistake in the code. It originally comes from the OpenWrt patches. Cc: Michael Buesch <mb@bu3sch.de> Cc: Felix Fietkau <nbd@openwrt.org> Cc: Florian Schirmer <jolt@tuxbox.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
Note that the BCM4710 does not support the wait instruction, this
is not a mistake in the code.
    
It originally comes from the OpenWrt patches.
    
Cc: Michael Buesch <mb@bu3sch.de>
Cc: Felix Fietkau <nbd@openwrt.org>
Cc: Florian Schirmer <jolt@tuxbox.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
[MIPS] PMC MSP71xx mips common 2007-07-10T16:33:03+00:00 Marc St-Jean stjeanma@pmc-sierra.com 2007-06-14T21:55:31+00:00 9267a30d1dc7dcd7cadb5eb6a5bbfed703feeefa Patch to add mips common support for the PMC-Sierra MSP71xx devices. Signed-off-by: Marc St-Jean <Marc_St-Jean@pmc-sierra.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
Patch to add mips common support for the PMC-Sierra MSP71xx devices.

Signed-off-by: Marc St-Jean <Marc_St-Jean@pmc-sierra.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
[MIPS] define Hit_Invalidate_I to Index_Invalidate_I for loongson2 2007-07-10T16:33:02+00:00 Fuxin Zhang zhangfx@lemote.com 2007-06-06T06:52:43+00:00 2a21c7300b53b744d16903256a172d9cbcfdd03e Signed-off-by: Fuxin Zhang <zhangfx@lemote.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
Signed-off-by: Fuxin Zhang <zhangfx@lemote.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
[MIPS] Enable support for the userlocal hardware register 2007-07-10T16:33:02+00:00 Ralf Baechle ralf@linux-mips.org 2007-07-10T16:33:02+00:00 a36920200c5b89d56120a5e839fe4a603d51b16c Which will cut down the cost of RDHWR $29 which is used to obtain the TLS pointer and so far being emulated in software down to a single cycle operation. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
Which will cut down the cost of RDHWR $29 which is used to obtain the
TLS pointer and so far being emulated in software down to a single cycle
operation.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>