linux-toradex.git/include/asm-mips/hazards.h, branch v2.6.17.3 Linux kernel for Apalis and Colibri modules [MIPS] MT: Improved multithreading support. 2006-04-19T02:14:28+00:00 Ralf Baechle ralf@linux-mips.org 2006-04-05T08:45:45+00:00 41c594ab65fc89573af296d192aa5235d09717ab Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
    
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
[MIPS] SB1: Fix interrupt disable hazard. 2006-03-18T16:59:26+00:00 Ralf Baechle ralf@linux-mips.org 2006-03-13T16:16:29+00:00 a3c4946db4fe64cb21b66a09e89890678aac6d65 The SB1 core has a three cycle interrupt disable hazard but we were wrongly treating it as fully interlocked. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
    
The SB1 core has a three cycle interrupt disable hazard but we were
wrongly treating it as fully interlocked.
    
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
[MIPS] Fix C version of ssnop to use the right opcode. 2006-02-07T13:30:21+00:00 Ralf Baechle ralf@linux-mips.org 2006-01-11T18:23:00+00:00 05faa7b758e4f23b66c5a776a338f2348cbbc4af Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
    
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
MIPS: R2: Try to bulletproof instruction_hazard against miss-compilation. 2006-01-10T13:39:08+00:00 Ralf Baechle ralf@linux-mips.org 2005-12-22T12:41:29+00:00 7043ad4f4c81914ca9e2cd2208c8f4801ed63735 Gcc has a tradition of misscompiling the previous construct using the address of a label as argument to inline assembler. Gas otoh has the annoying difference between la and dla which are only usable for 32-bit rsp. 64-bit code, so can't be used without conditional compilation. The alterantive is switching the assembler to 64-bit code which happens to work right even for 32-bit code ... Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
    
Gcc has a tradition of misscompiling the previous construct using the
address of a label as argument to inline assembler.  Gas otoh has the
annoying difference between la and dla which are only usable for 32-bit
rsp. 64-bit code, so can't be used without conditional compilation.
The alterantive is switching the assembler to 64-bit code which happens
to work right even for 32-bit code ...
    
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Fixup a few lose ends in explicit support for MIPS R1/R2. 2005-10-29T18:32:37+00:00 Ralf Baechle ralf@linux-mips.org 2005-10-07T15:58:15+00:00 ec917c2c1ab4359a1d438e62daeb50cc42e632e1 Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
    
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Use R4000 TLB routines for SB1 also. 2005-10-29T18:32:31+00:00 Ralf Baechle ralf@linux-mips.org 2005-10-01T10:14:17+00:00 f5cfa980e535e1f77038f8037422594592208695 Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Cleanups. 2005-10-29T18:31:53+00:00 Ralf Baechle ralf@linux-mips.org 2005-07-14T13:25:05+00:00 86071b637db7baf599df26fdf820dce2fc55ca9f Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
MIPS R2 instruction hazard handling. 2005-10-29T18:31:46+00:00 Ralf Baechle ralf@linux-mips.org 2005-07-12T18:35:38+00:00 cc61c1fede7d02cb8133ab0952ca3f3ba1f7fbb1 Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
One definition of back_to_back_c0_hazard too much. 2005-10-29T18:30:50+00:00 Ralf Baechle ralf@linux-mips.org 2005-03-02T19:18:46+00:00 88d535b6b58632bc51ee9a1f35ddfc357e365c37 Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
New hazard handling function back_to_back_c0_hazard() to handle back to 2005-10-29T18:30:49+00:00 Ralf Baechle ralf@linux-mips.org 2005-03-01T18:12:06+00:00 5068debff2dcbc8f624811e3c06d60c7c0bba744 back mtc0 / mfc0 pairs from the same coprocessor register. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
back mtc0 / mfc0 pairs from the same coprocessor register.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>