<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux-toradex.git/include/asm-mips/hazards.h, branch v2.6.22.5</title>
<subtitle>Linux kernel for Apalis and Colibri modules</subtitle>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/'/>
<entry>
<title>[MIPS] SB1: Build fix.</title>
<updated>2007-05-11T13:28:31+00:00</updated>
<author>
<name>Ralf Baechle</name>
<email>ralf@linux-mips.org</email>
</author>
<published>2007-05-09T16:49:53+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=a1b53a7b22934504d8c4e065759e8674e665506d'/>
<id>a1b53a7b22934504d8c4e065759e8674e665506d</id>
<content type='text'>
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>[MIPS] FPU hazard handling</title>
<updated>2007-05-11T13:28:31+00:00</updated>
<author>
<name>Chris Dearman</name>
<email>chris@mips.com</email>
</author>
<published>2007-05-08T15:09:13+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=0b6249567b4ecf6e9d5a8efcf149f3e7cf788cc0'/>
<id>0b6249567b4ecf6e9d5a8efcf149f3e7cf788cc0</id>
<content type='text'>
Move FPU hazard handling to hazards.h and provide proper support for
MIPSR2 processors

Signed-off-by: Chris Dearman &lt;chris@mips.com&gt;
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Move FPU hazard handling to hazards.h and provide proper support for
MIPSR2 processors

Signed-off-by: Chris Dearman &lt;chris@mips.com&gt;
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>[MIPS] Fix pipeline hazard.</title>
<updated>2007-03-24T17:01:49+00:00</updated>
<author>
<name>Ralf Baechle</name>
<email>ralf@linux-mips.org</email>
</author>
<published>2007-03-20T13:56:50+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=7605b3906192a171e651076325b1ed1d5ea57ec9'/>
<id>7605b3906192a171e651076325b1ed1d5ea57ec9</id>
<content type='text'>
In the the sequence:
        ei
        ..
        mfc0    $x, $status

the mfc0 may not see the SR_IE bit set. This was a deliberate bug in the
kernel code because we knew this was a safe thing to do on all R2 silicon
so far but new silicon is changing this.

Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
In the the sequence:
        ei
        ..
        mfc0    $x, $status

the mfc0 may not see the SR_IE bit set. This was a deliberate bug in the
kernel code because we knew this was a safe thing to do on all R2 silicon
so far but new silicon is changing this.

Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>[MIPS] vr41xx: need one more nop with mtc0_tlbw_hazard()</title>
<updated>2007-01-24T19:23:21+00:00</updated>
<author>
<name>Yoichi Yuasa</name>
<email>yoichi_yuasa@tripeaks.co.jp</email>
</author>
<published>2007-01-24T13:22:06+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=3f3183709feb35c30ca5f649224d01921870f81c'/>
<id>3f3183709feb35c30ca5f649224d01921870f81c</id>
<content type='text'>
NEC VR4111 and VR4121 need one more nop with mtc0_tlbw_hazard().

Signed-off-by: Yoichi Yuasa &lt;yoichi_yuasa@tripeaks.co.jp&gt;
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
NEC VR4111 and VR4121 need one more nop with mtc0_tlbw_hazard().

Signed-off-by: Yoichi Yuasa &lt;yoichi_yuasa@tripeaks.co.jp&gt;
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>[MIPS] s/__ASSEMBLER__/__ASSEMBLY__/ for clarity sake.</title>
<updated>2006-09-27T12:37:57+00:00</updated>
<author>
<name>Ralf Baechle</name>
<email>ralf@linux-mips.org</email>
</author>
<published>2006-09-25T14:49:49+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=36396f3c36b04f79438f87a0fccfa76aa3de6af9'/>
<id>36396f3c36b04f79438f87a0fccfa76aa3de6af9</id>
<content type='text'>
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>[MIPS] Cleanup hazard handling.</title>
<updated>2006-09-27T12:37:53+00:00</updated>
<author>
<name>Ralf Baechle</name>
<email>ralf@linux-mips.org</email>
</author>
<published>2006-09-08T02:13:49+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=d7d86aa88a1f3922b85e39edd8a6d6c01e939842'/>
<id>d7d86aa88a1f3922b85e39edd8a6d6c01e939842</id>
<content type='text'>
Mostly based on patch by Chris Dearman and cleanups from Yoichi.

Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Mostly based on patch by Chris Dearman and cleanups from Yoichi.

Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>[MIPS] Add missing backslashes to macro definitions.</title>
<updated>2006-06-29T20:10:55+00:00</updated>
<author>
<name>Ralf Baechle</name>
<email>ralf@linux-mips.org</email>
</author>
<published>2006-06-29T19:06:53+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=8db089c6b5594c961fb6bc6d613b9926e0d3d98f'/>
<id>8db089c6b5594c961fb6bc6d613b9926e0d3d98f</id>
<content type='text'>
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Don't include linux/config.h from anywhere else in include/</title>
<updated>2006-04-26T11:56:16+00:00</updated>
<author>
<name>David Woodhouse</name>
<email>dwmw2@infradead.org</email>
</author>
<published>2006-04-26T11:56:16+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=62c4f0a2d5a188f73a94f2cb8ea0dba3e7cf0a7f'/>
<id>62c4f0a2d5a188f73a94f2cb8ea0dba3e7cf0a7f</id>
<content type='text'>
Signed-off-by: David Woodhouse &lt;dwmw2@infradead.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Signed-off-by: David Woodhouse &lt;dwmw2@infradead.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>[MIPS] MT: Improved multithreading support.</title>
<updated>2006-04-19T02:14:28+00:00</updated>
<author>
<name>Ralf Baechle</name>
<email>ralf@linux-mips.org</email>
</author>
<published>2006-04-05T08:45:45+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=41c594ab65fc89573af296d192aa5235d09717ab'/>
<id>41c594ab65fc89573af296d192aa5235d09717ab</id>
<content type='text'>
    
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
    
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>[MIPS] SB1: Fix interrupt disable hazard.</title>
<updated>2006-03-18T16:59:26+00:00</updated>
<author>
<name>Ralf Baechle</name>
<email>ralf@linux-mips.org</email>
</author>
<published>2006-03-13T16:16:29+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=a3c4946db4fe64cb21b66a09e89890678aac6d65'/>
<id>a3c4946db4fe64cb21b66a09e89890678aac6d65</id>
<content type='text'>
    
The SB1 core has a three cycle interrupt disable hazard but we were
wrongly treating it as fully interlocked.
    
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
    
The SB1 core has a three cycle interrupt disable hazard but we were
wrongly treating it as fully interlocked.
    
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</pre>
</div>
</content>
</entry>
</feed>
