linux-toradex.git/include/asm-mips, branch v2.6.16.50

[PATCH] SPARC64: Fix D-cache corruption in mremap

2006-06-22T19:16:11+00:00

If we move a mapping from one virtual address to another,
and this changes the virtual color of the mapping to those
pages, we can see corrupt data due to D-cache aliasing.

Check for and deal with this by overriding the move_pte()
macro.  Set things up so that other platforms can cleanly
override the move_pte() macro too.

This long standing bug corrupts user memory, and in particular
has been notorious for corrupting Debian package database
files on sparc64 boxes.

Signed-off-by: David S. Miller 
Signed-off-by: Chris Wright 
Signed-off-by: Greg Kroah-Hartman

[PATCH] MIPS: R2 build fixes for gcc < 3.4.

2006-05-01T19:03:44+00:00

Signed-off-by: Ralf Baechle 
Signed-off-by: Greg Kroah-Hartman

[PATCH] MIPS: Use "R" constraint for cache_op.

2006-05-01T19:03:44+00:00

Gcc might emit an absolute address for the the "m" constraint which
gas unfortunately does not permit.

Signed-off-by: Ralf Baechle 
Signed-off-by: Greg Kroah-Hartman

[MIPS] Sibyte: Fix race in sb1250_gettimeoffset().

2006-03-18T16:59:30+00:00

    
From Dave Johnson :
    
sb1250_gettimeoffset() simply reads the current cpu 0 timer remaining
value, however once this counter reaches 0 and the interrupt is raised,
it immediately resets and begins to count down again.
    
If sb1250_gettimeoffset() is called on cpu 1 via do_gettimeofday() after
the timer has reset but prior to cpu 0 processing the interrupt and
taking write_seqlock() in timer_interrupt() it will return a full value
(or close to it) causing time to jump backwards 1ms. Once cpu 0 handles
the interrupt and timer_interrupt() gets far enough along it will jump
forward 1ms.
    
Fix this problem by implementing mips_hpt_*() on sb1250 using a spare
timer unrelated to the existing periodic interrupt timers. It runs at
1Mhz with a full 23bit counter.  This eliminated the custom
do_gettimeoffset() for sb1250 and allowed use of the generic
fixed_rate_gettimeoffset() using mips_hpt_*() and timerhi/timerlo.
    
Signed-off-by: Ralf Baechle

[MIPS] Sibyte: Fix M_SCD_TIMER_INIT and M_SCD_TIMER_CNT wrong field width.

2006-03-18T16:59:29+00:00

    
From Dave Johnson :
    
Field width should be 23 bits not 20 bits.
    
Signed-off-by: Ralf Baechle

[MIPS] Work around bad code generation for .

2006-03-18T16:59:28+00:00

    
If a call to set_io_port_base() was being followed by usage of
mips_io_port_base in the same function gcc was possibly using the old
value due to some clever abuse of const.  Adding a barrier will keep
the optimization and result in correct code with latest gcc.
    
Signed-off-by: Ralf Baechle

[MIPS] local_r4k_flush_cache_page fix

2006-03-18T16:59:27+00:00

    
If dcache_size != icache_size or dcache_size != scache_size, or
set-associative cache, icache/scache does not flushed properly.  Make
blast_?cache_page_indexed() masks its index value correctly.  Also,
use physical address for physically indexed pcache/scache.
    
Signed-off-by: Atsushi Nemoto 
Signed-off-by: Ralf Baechle

[MIPS] SB1: Fix interrupt disable hazard.

2006-03-18T16:59:26+00:00

    
The SB1 core has a three cycle interrupt disable hazard but we were
wrongly treating it as fully interlocked.
    
Signed-off-by: Ralf Baechle

[MIPS] Undefine scr_writew and scr_readw in .

2006-03-09T18:05:10+00:00

    
This is gluing the build of cirrusfb but really the mess that would need
cleaning and fixing is  and  ...
    
Signed-off-by: Ralf Baechle

[MIPS] Fix build error on processors that don's support copy-on-write.

2006-02-28T17:04:20+00:00

Signed-off-by: Ralf Baechle