linux-toradex.git/include/asm-powerpc/reg.h, branch v2.6.19.2

[POWERPC] Cell timebase bug workaround

2006-10-25T01:54:18+00:00

The Cell CPU timebase has an erratum. When reading the entire 64 bits
of the timebase with one mftb instruction, there is a handful of cycles
window during which one might read a value with the low order 32 bits
already reset to 0x00000000 but the high order bits not yet incremeted
by one. This fixes it by reading the timebase again until the low order
32 bits is no longer 0. That might introduce occasional latencies if
hitting mftb just at the wrong time, but no more than 70ns on a cell
blade, and that was considered acceptable.

Signed-off-by: Benjamin Herrenschmidt 
Acked-by: Olof Johansson 
Signed-off-by: Paul Mackerras

[POWERPC] Add 970GX cputable entry

2006-10-23T08:23:17+00:00

970GX cputable entry from Steve Winiecki.

Signed-off-by: Jake Moilanen 

 arch/powerpc/kernel/cputable.c          |   15 +++++++++++++++
 arch/powerpc/oprofile/op_model_power4.c |    2 +-
 include/asm-powerpc/reg.h               |    1 +
 3 files changed, 17 insertions(+), 1 deletion(-)
Signed-off-by: Paul Mackerras

[POWERPC] Update MTFSF_L() comment

2006-10-06T11:10:41+00:00

David Woodhouse points out that the comment accompanying the MTFSF_L
macro is misleading. We should make it clear that the L bit is ignored
on older CPUS, not the entire instruction.

Signed-off-by: Anton Blanchard 
Signed-off-by: Paul Mackerras

[POWERPC] powerpc: PA6T cputable entry, PVR value

2006-09-13T08:39:52+00:00

Introduce PWRficient PA6T cputable entries and feature bits.

Signed-off-by: Olof Johansson 
Signed-off-by: Paul Mackerras

[POWERPC] cell: add RAS support

2006-06-21T05:01:29+00:00

This is a first version of support for the Cell BE "Reliability,
Availability and Serviceability" features.

It doesn't yet handle some of the RAS interrupts (the ones described in
iic_is/iic_irr), I'm still working on a proper way to expose these. They
are essentially a cascaded controller by themselves (sic !) though I may
just handle them locally to the iic driver. I need also to sync with
David Erb on the way he hooked in the performance monitor interrupt.

So that's all for 2.6.17 and I'll do more work on that with my rework of
the powerpc interrupt layer that I'm hacking on at the moment.

Signed-off-by: Arnd Bergmann 
Signed-off-by: Paul Mackerras

[POWERPC] Fix HV bit handling on non partitioned machines

2006-06-15T09:31:26+00:00

On non partitioned machines we currently set the HV bit in kernel space
only. It turns out we are supposed to maintain the HV bit in both user
and kernel space.

Signed-off-by: Anton Blanchard 
Signed-off-by: Paul Mackerras

[POWERPC] 64bit FPSCR support

2006-06-15T09:31:25+00:00

Forthcoming machines will extend the FPSCR to 64 bits.  We already
had a 64-bit save area for the FPSCR, but we need to use a new form
of the mtfsf instruction.  Fortunately this new form is decoded as
an ordinary mtfsf by existing 64-bit processors.

Signed-off-by: Anton Blanchard 
Signed-off-by: Paul Mackerras

[PATCH] powerpc: oprofile support for POWER6

2006-06-09T11:24:05+00:00

POWER6 moves some of the MMCRA bits and also requires some bits to be
cleared each PMU interrupt.

Signed-off-by: Michael Neuling 
Acked-by: Anton Blanchard 
Signed-off-by: Paul Mackerras

[PATCH] powerpc: whitespace cleanup in reg.h

2006-05-19T04:35:25+00:00

In reg.h we mostly have #define but there are a few #define
around.  Clean these up so we use space exclusively.

Signed-off-by: Michael Neuling 
Signed-off-by: Paul Mackerras

powerpc: Unify the 32 and 64 bit idle loops

2006-03-27T04:03:03+00:00

This unifies the 32-bit (ARCH=ppc and ARCH=powerpc) and 64-bit idle
loops.  It brings over the concept of having a ppc_md.power_save
function from 32-bit to ARCH=powerpc, which lets us get rid of
native_idle().  With this we will also be able to simplify the idle
handling for pSeries and cell.

Signed-off-by: Paul Mackerras