linux-toradex.git/include/asm-powerpc, branch v2.6.17.10

[PATCH] powerpc: enable CPU_FTR_CI_LARGE_PAGE for cell

2006-06-17T17:56:24+00:00

Reflect the fact that the Cell Broadband Engine supports 64k
pages by adding the bit to the CPU features.

Signed-off-by: Arnd Bergmann 
Signed-off-by: Linus Torvalds

[PATCH] Add CMSPAR to termbits.h for powerpc and alpha

2006-05-26T18:55:46+00:00

Some driver wants to use CMSPAR, but it was missing on alpha and powerpc.
This adds it, with the same value as every other architecture uses.

(akpm: fixes the build of an upcoming gregkh USB patch)

Signed-off-by: Paul Mackerras 
Cc: Richard Henderson 
Cc: Ivan Kokshaysky 
Cc: Greg KH 
Signed-off-by: Andrew Morton 
Signed-off-by: Linus Torvalds

[PATCH] powerpc: wire up sys_[gs]et_robust_list

2006-05-23T17:35:32+00:00

Signed-off-by: David Woodhouse 
Cc: Benjamin Herrenschmidt 
Acked-by: Paul Mackerras 
Cc: Arnd Bergmann 
Signed-off-by: Andrew Morton 
Signed-off-by: Linus Torvalds

powerpc: Fix incorrect might_sleep in __get_user/__put_user on kernel addresses

2006-05-03T13:06:46+00:00

We have a case where __get_user and __put_user can validly be used
on kernel addresses in interrupt context - namely, the alignment
exception handler, as our get/put_unaligned just do a single access
and rely on the alignment exception handler to fix things up in the
rare cases where the cpu can't handle it in hardware.  Thus we can
get alignment exceptions in the network stack at interrupt level.
The alignment exception handler does a __get_user to read the
instruction and blows up in might_sleep().

Since a __get_user on a kernel address won't actually ever sleep,
this makes the might_sleep conditional on the address being less
than PAGE_OFFSET.

Signed-off-by: Paul Mackerras

[PATCH] powerpc: cell: Add numa id to struct spu

2006-05-02T01:17:46+00:00

Add an nid member to the spu structure, and store the numa id of the spu there
on creation.

Signed-off-by: Arnd Bergmann 
Cc: Paul Mackerras 
Signed-off-by: Andrew Morton 
Signed-off-by: Linus Torvalds

[PATCH] powerpc: Allow devices to register with numa topology

2006-05-02T01:17:46+00:00

Change of_node_to_nid() to traverse the device tree, looking for a numa id.
Cell uses this to assign ids to SPUs, which are children of the CPU node.
Existing users of of_node_to_nid() are altered to use of_node_to_nid_single(),
which doesn't do the traversal.

Export an attach_sysdev_to_node() function, allowing system devices (eg.
SPUs) to link themselves into the numa topology in sysfs.

Signed-off-by: Arnd Bergmann 
Cc: Paul Mackerras 
Signed-off-by: Andrew Morton 
Signed-off-by: Linus Torvalds

[PATCH] powerpc: Add cputable entry for POWER6

2006-04-29T00:56:58+00:00

Add a cputable entry for the POWER6 processor.

The SIHV and SIPR bits in the mmcra have moved in POWER6, so disable
support for that until oprofile is fixed.

Also tell firmware that we know about POWER6.

Signed-off-by: Anton Blanchard 
Signed-off-by: Paul Mackerras

[PATCH] powerpc: Wire up *at syscalls

2006-04-28T11:04:59+00:00

Wire up *at syscalls.

This patch has been tested on ppc64 (using glibc's testsuite, both 32bit
and 64bit), and compile-tested for ppc32 (I have currently no ppc32 system
available, but I expect no problems).

Signed-off-by: Andreas Schwab 
Signed-off-by: Paul Mackerras

[PATCH] powerpc: Use check_legacy_ioport() on ppc32 too.

2006-04-28T11:04:55+00:00

Some people report that we die on some Macs when we are expecting to
catch machine checks after poking at some random I/O address. I'd seen
it happen on my dual G4 with serial ports until we fixed those to use
OF, but now other users are reporting it with i8042.

This expands the use of check_legacy_ioport() to avoid that situation
even on 32-bit kernels.

Signed-off-by: David Woodhouse 
Signed-off-by: Paul Mackerras

[PATCH] powerpc: Fix pagetable bloat for hugepages

2006-04-28T05:02:51+00:00

At present, ARCH=powerpc kernels can waste considerable space in
pagetables when making large hugepage mappings.  Hugepage PTEs go in
PMD pages, but each PMD page maps 256M and so contains only 16
hugepage PTEs (128 bytes of data), but takes up a 1024 byte
allocation.  With CONFIG_PPC_64K_PAGES enabled (64k base page size),
the situation is worse.  Now hugepage PTEs are at the PTE page level
(also mapping 256M), so we store 16 hugepage PTEs in a 64k allocation.

The PowerPC MMU already means that any 256M region is either all
hugepage, or all normal pages.  Thus, with some care, we can use a
different allocation for the hugepage PTE tables and only allocate the
128 bytes necessary.

Signed-off-by: Paul Mackerras