linux-toradex.git/include/asm-ppc/reg_booke.h, branch v2.6.24.3

[POWERPC] Compile fixes for arch/powerpc dcr code

2007-02-07T03:03:23+00:00

The new dcr code does not currently compile when configured for native
DCR access on ARCH=powerpc.  This patch fixes the problems.

Signed-off-by: David Gibson 
Signed-off-by: Paul Mackerras

[POWERPC] Only export mtdcr/mfdcr if CONFIG_PPC_DCR is set

2006-12-11T05:15:47+00:00

On 85xx we don't build in dcr support because the core doesn't implement the
instructions.  This caused problems when building an 85xx kernel.  Additionally
made it so we only build __mtdcr/__mfdcr if we are CONFIG_PPC_DCR_NATIVE.

The 85xx build issue wasPointed out by Dai Haruki.

Signed-off-by: Kumar Gala

[POWERPC] 40x: Fix debug status register defines

2006-09-21T12:59:39+00:00

This fixes some debug register defines on PPC 40x that were incorrect.

Signed-off-by: Josh Boyer 
Signed-off-by: Paul Mackerras

[PATCH] ppc32: add 440GX erratum 440_43 workaround

2006-04-28T11:04:56+00:00

This patch adds workaround for PPC 440GX erratum 440_43. According to
this erratum spurious MachineChecks (caused by L1 cache parity) can
happen during DataTLB miss processing. We disable L1 cache parity
checking for 440GX rev.C and rev.F

Signed-off-by: Eugene Surovegin 
Signed-off-by: Paul Mackerras

[PATCH] ppc32: Add support for Freescale e200 (Book-E) core

2005-06-25T23:24:26+00:00

The e200 core is a Book-E core (similar to e500) that has a unified L1 cache
and is not cache coherent on the bus.  The e200 core also adds a separate
exception level for debug exceptions.  Part of this patch helps to cleanup a
few cases that are true for all Freescale Book-E parts, not just e500.

Signed-off-by: Kim Phillips 
Signed-off-by: Kumar Gala 
Signed-off-by: Andrew Morton 
Signed-off-by: Linus Torvalds

[PATCH] ppc32: refactor FPU exception handling

2005-05-01T15:58:40+00:00

Moved common FPU exception handling code out of head.S so it can be used by
several of the sub-architectures that might of a full PowerPC FPU.

Also, uses new CONFIG_PPC_FPU define to fix alignment exception handling
for floating point load/store instructions to only occur if we have a
hardware FPU.

Signed-off-by: Jason McMullan 
Signed-off-by: Kumar Gala 
Signed-off-by: Paul Mackerras 
Signed-off-by: Andrew Morton 
Signed-off-by: Linus Torvalds

[PATCH] ppc32: Support 36-bit physical addressing on e500

2005-04-16T22:24:22+00:00

To add support for 36-bit physical addressing on e500 the following changes
have been made.  The changes are generalized to support any physical address
size larger than 32-bits:

* Allow FSL Book-E parts to use a 64-bit PTE, it is 44-bits of pfn, 20-bits
  of flags.

* Introduced new CPU feature (CPU_FTR_BIG_PHYS) to allow runtime handling of
  updating hardware register (SPRN_MAS7) which holds the upper 32-bits of
  physical address that will be written into the TLB.  This is useful since
  not all e500 cores support 36-bit physical addressing.

* Currently have a pass through implementation of fixup_bigphys_addr

* Moved _PAGE_DIRTY in the 64-bit PTE case to free room for three additional
  storage attributes that may exist in future FSL Book-E cores and updated
  fault handler to copy these bits into the hardware TLBs.

Signed-off-by: Kumar Gala 
Signed-off-by: Andrew Morton 
Signed-off-by: Linus Torvalds

Linux-2.6.12-rc2

2005-04-16T22:20:36+00:00

Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.

Let it rip!