linux-toradex.git/include/dt-bindings/clock/microchip,mpfs-clock.h, branch v6.4-rc6 Linux kernel for Apalis and Colibri modules dt-bindings: clk: add PolarFire SoC fabric clock ids 2022-09-14T07:57:07+00:00 Conor Dooley conor.dooley@microchip.com 2022-09-08T14:36:50+00:00 b4b025246c0fbb8611a26bab121596f47f0bf116 Each Clock Conditioning Circuitry block contains 2 PLLs and 2 DLLs. The PLLs have 4 outputs each and the DLLs 2. Add 16 new IDs covering these clocks. For more information on the CCC hardware, see the "PolarFire SoC FPGA Clocking Resources" document at the link below. Link: https://onlinedocs.microchip.com/pr/GUID-8F0CC4C0-0317-4262-89CA-CE7773ED1931-en-US-1/index.html Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220908143651.1252601-4-conor.dooley@microchip.com 
Each Clock Conditioning Circuitry block contains 2 PLLs and 2 DLLs.
The PLLs have 4 outputs each and the DLLs 2. Add 16 new IDs covering
these clocks. For more information on the CCC hardware, see the
"PolarFire SoC FPGA Clocking Resources" document at the link below.

Link: https://onlinedocs.microchip.com/pr/GUID-8F0CC4C0-0317-4262-89CA-CE7773ED1931-en-US-1/index.html
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220908143651.1252601-4-conor.dooley@microchip.com
dt-bindings: clk: mpfs: add defines for two new clocks 2022-04-23T01:40:15+00:00 Conor Dooley conor.dooley@microchip.com 2022-04-13T07:58:32+00:00 8be99c7b8bb17f2b82af4a0a6798b795f4d74436 The RTC reference and MSSPLL were previously not documented or defined, as they were unused. Add their defines to the PolarFire SoC header. Fixes: 2145bb687e3f ("dt-bindings: clk: microchip: Add Microchip PolarFire host binding") Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220413075835.3354193-6-conor.dooley@microchip.com Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org> 
The RTC reference and MSSPLL were previously not documented or defined,
as they were unused. Add their defines to the PolarFire SoC header.

Fixes: 2145bb687e3f ("dt-bindings: clk: microchip: Add Microchip PolarFire host binding")
Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20220413075835.3354193-6-conor.dooley@microchip.com
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
dt-bindings: clk: microchip: Add Microchip PolarFire host binding 2022-01-25T00:25:59+00:00 Daire McNamara daire.mcnamara@microchip.com 2021-12-16T14:00:21+00:00 2145bb687e3fdb128066872fd952f4563d89177e Add device tree bindings for the Microchip PolarFire system clock controller Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20211216140022.16146-2-conor.dooley@microchip.com Signed-off-by: Stephen Boyd <sboyd@kernel.org> 
Add device tree bindings for the Microchip PolarFire system
clock controller

Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20211216140022.16146-2-conor.dooley@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>