linux-toradex.git/include/dt-bindings/phy, branch v5.11-rc2

dt-bindings: phy: Add PHY_TYPE_QSGMII definition

2020-09-18T05:17:19+00:00

Add definition for QSGMII phy type.

Signed-off-by: Swapnil Jakhade 
Acked-by: Rob Herring 
Link: https://lore.kernel.org/r/1600327846-9733-5-git-send-email-sjakhade@cadence.com
Signed-off-by: Vinod Koul

dt-bindings: phy: cadence-torrent: Add binding to specify SSC mode

2020-09-18T05:04:48+00:00

Add binding to specify Spread Spectrum Clocking mode used.

Signed-off-by: Swapnil Jakhade 
Reviewed-by: Rob Herring 
Link: https://lore.kernel.org/r/1600280911-9214-7-git-send-email-sjakhade@cadence.com
Signed-off-by: Vinod Koul

dt-bindings: phy: Add DT bindings for Xilinx ZynqMP PSGTR PHY

2020-06-29T13:18:00+00:00

Add DT bindings for the Xilinx ZynqMP PHY. ZynqMP SoCs have a High Speed
Processing System Gigabit Transceiver which provides PHY capabilities to
USB, SATA, PCIE, Display Port and Ehernet SGMII controllers.

Signed-off-by: Anurag Kumar Vulisha 
Signed-off-by: Laurent Pinchart 
Reviewed-by: Rob Herring 
Link: https://lore.kernel.org/r/20200629120054.29338-2-laurent.pinchart@ideasonboard.com
Signed-off-by: Vinod Koul

dt-bindings: phy: Add PHY_TYPE_XPCS definition

2020-05-19T14:56:06+00:00

Add definition for Ethernet PCS phy type.

Signed-off-by: Dilip Kota 
Acked-by: Rob Herring 
Acked-By: Vinod Koul 
Link: https://lore.kernel.org/r/6091f0d2a1046f1e3656d9e33b6cc433d5465eaf.1589868358.git.eswara.kota@linux.intel.com
Signed-off-by: Kishon Vijay Abraham I

dt-bindings: phy: Add PHY_TYPE_DP definition

2020-01-17T05:24:35+00:00

Add definition for DisplayPort phy type.

Signed-off-by: Jyri Sarha 
Reviewed-by: Roger Quadros 
Reviewed-by: Kishon Vijay Abraham I 
Signed-off-by: Kishon Vijay Abraham I

dt-bindings: phy: add binding for the Lantiq VRX200 and ARX300 PCIe PHYs

2019-08-23T04:10:46+00:00

Add the bindings for the PCIe PHY on Lantiq VRX200 and ARX300 SoCs.
The IP block contains settings for the PHY and a PLL.
The PLL mode is configurable through a dedicated #phy-cell in .dts.

Signed-off-by: Martin Blumenstingl 
Reviewed-by: Rob Herring 
Signed-off-by: Kishon Vijay Abraham I

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 422

2019-06-05T15:37:15+00:00

Based on 1 normalized pattern(s):

  this program is free software you can redistribute it and or modify
  it under the terms and conditions of the gnu general public license
  version 2 as published by the free software foundation

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-only

has been chosen to replace the boilerplate/reference in 101 file(s).

Signed-off-by: Thomas Gleixner 
Reviewed-by: Allison Randal 
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190531190113.822954939@linutronix.de
Signed-off-by: Greg Kroah-Hartman

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 194

2019-05-30T18:29:22+00:00

Based on 1 normalized pattern(s):

  license terms gnu general public license gpl version 2

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-only

has been chosen to replace the boilerplate/reference in 161 file(s).

Signed-off-by: Thomas Gleixner 
Reviewed-by: Allison Randal 
Reviewed-by: Alexios Zavras 
Reviewed-by: Steve Winslow 
Reviewed-by: Richard Fontana 
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190528170027.447718015@linutronix.de
Signed-off-by: Greg Kroah-Hartman

dt-bindings: phy: ti: Add dt binding documentation for SERDES in AM654x SoC

2019-04-17T08:43:18+00:00

AM654x has two SERDES instances. Each instance has three input clocks
(left input, externel reference clock and right input) and two output
clocks (left output and right output) in addition to a PLL mux clock
which the SERDES uses for Clock Multiplier Unit (CMU refclock).
The PLL mux clock can select from one of the three input clocks.
The right output can select between left input and external reference
clock while the left output can select between the right input and
external reference clock.

The left and right input reference clock of SERDES0 and SERDES1
respectively are connected to the SoC clock. In the case of two lane
SERDES personality card, the left input of SERDES1 is connected to
the right output of SERDES0 in a chained fashion.

See section "Reference Clock Distribution" of AM65x Sitara Processors
TRM (SPRUID7 – April 2018) for more details.

Add dt-binding documentation in order to represent all these different
configurations in device tree.

Signed-off-by: Kishon Vijay Abraham I

dt-bindings: phy: Update SERDES_MAX to be SERDES_MAX + 1

2018-10-23T02:27:14+00:00

SERDES_MAX is a valid value to index ctrl->phys in
drivers/phy/mscc/phy-ocelot-serdes.c. But, currently,
there is an out-of-bounds bug in the mentioned driver
when reading from ctrl->phys, because the size of
array ctrl->phys is SERDES_MAX.

Partially fix this by updating SERDES_MAX to be SERDES6G_MAX + 1.

Notice that this is the first part of the solution to
the out-of-bounds bug mentioned above. Although this
change is not dependent on any other one.

Suggested-by: Quentin Schulz 
Reviewed-by: Quentin Schulz 
Acked-by: Rob Herring 
Signed-off-by: Gustavo A. R. Silva 
Signed-off-by: David S. Miller