linux-toradex.git/include/dt-bindings/phy, branch v5.15-rc5

dt-bindings: msm: dsi: document phy-type property for 7nm dsi phy

2021-08-07T18:48:37+00:00

Document a new phy-type property which will be used to determine whether
the phy should operate in D-PHY or C-PHY mode.

Signed-off-by: Jonathan Marek 
Reviewed-by: Laurent Pinchart 
Link: https://lore.kernel.org/r/20210617144349.28448-3-jonathan@marek.ca
Acked-by: Rob Herring 
Signed-off-by: Dmitry Baryshkov 
Signed-off-by: Rob Clark

dt-bindings: phy: phy-cadence-sierra: Add binding to model Sierra as clock provider

2021-03-31T11:13:21+00:00

Add #clock-cells binding to model Sierra as clock provider and include
clock IDs for PLL_CMNLC and PLL_CMNLC1.

Signed-off-by: Kishon Vijay Abraham I 
Reviewed-by: Rob Herring 
Link: https://lore.kernel.org/r/20210319124128.13308-12-kishon@ti.com
Signed-off-by: Vinod Koul

phy: cadence-torrent: Use a common header file for Cadence SERDES

2021-03-31T11:13:20+00:00

No functional change. In order to have a single header file for all
Cadence SERDES move phy-cadence-torrent.h to phy-cadence.h. This is
in preparation for adding Cadence Sierra SERDES specific macros.

Signed-off-by: Kishon Vijay Abraham I 
Reviewed-by: Swapnil Jakhade 
Acked-by: Rob Herring 
Link: https://lore.kernel.org/r/20210319124128.13308-9-kishon@ti.com
Signed-off-by: Vinod Koul

dt-bindings: phy: cadence-torrent: Add binding for refclk driver

2021-03-17T06:32:40+00:00

Add binding for refclk driver used to route the refclk out of torrent
SERDES.

Signed-off-by: Kishon Vijay Abraham I 
Reviewed-by: Rob Herring 
Link: https://lore.kernel.org/r/20210310112745.3445-3-kishon@ti.com
Signed-off-by: Vinod Koul

dt-bindings: phy: ti,phy-j721e-wiz: Add bindings for AM64 SERDES Wrapper

2021-03-17T06:32:40+00:00

Add bindings for AM64 SERDES Wrapper.

Signed-off-by: Kishon Vijay Abraham I 
Reviewed-by: Rob Herring 
Link: https://lore.kernel.org/r/20210310112745.3445-2-kishon@ti.com
Signed-off-by: Vinod Koul

dt-bindings: phy: Add PHY_TYPE_QSGMII definition

2020-09-18T05:17:19+00:00

Add definition for QSGMII phy type.

Signed-off-by: Swapnil Jakhade 
Acked-by: Rob Herring 
Link: https://lore.kernel.org/r/1600327846-9733-5-git-send-email-sjakhade@cadence.com
Signed-off-by: Vinod Koul

dt-bindings: phy: cadence-torrent: Add binding to specify SSC mode

2020-09-18T05:04:48+00:00

Add binding to specify Spread Spectrum Clocking mode used.

Signed-off-by: Swapnil Jakhade 
Reviewed-by: Rob Herring 
Link: https://lore.kernel.org/r/1600280911-9214-7-git-send-email-sjakhade@cadence.com
Signed-off-by: Vinod Koul

dt-bindings: phy: Add DT bindings for Xilinx ZynqMP PSGTR PHY

2020-06-29T13:18:00+00:00

Add DT bindings for the Xilinx ZynqMP PHY. ZynqMP SoCs have a High Speed
Processing System Gigabit Transceiver which provides PHY capabilities to
USB, SATA, PCIE, Display Port and Ehernet SGMII controllers.

Signed-off-by: Anurag Kumar Vulisha 
Signed-off-by: Laurent Pinchart 
Reviewed-by: Rob Herring 
Link: https://lore.kernel.org/r/20200629120054.29338-2-laurent.pinchart@ideasonboard.com
Signed-off-by: Vinod Koul

dt-bindings: phy: Add PHY_TYPE_XPCS definition

2020-05-19T14:56:06+00:00

Add definition for Ethernet PCS phy type.

Signed-off-by: Dilip Kota 
Acked-by: Rob Herring 
Acked-By: Vinod Koul 
Link: https://lore.kernel.org/r/6091f0d2a1046f1e3656d9e33b6cc433d5465eaf.1589868358.git.eswara.kota@linux.intel.com
Signed-off-by: Kishon Vijay Abraham I

dt-bindings: phy: Add PHY_TYPE_DP definition

2020-01-17T05:24:35+00:00

Add definition for DisplayPort phy type.

Signed-off-by: Jyri Sarha 
Reviewed-by: Roger Quadros 
Reviewed-by: Kishon Vijay Abraham I 
Signed-off-by: Kishon Vijay Abraham I