linux-toradex.git/include/dt-bindings/reset, branch master Linux kernel for Apalis and Colibri modules Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux 2026-10-30T16:18:43+00:00 Linus Torvalds torvalds@linux-foundation.org 2026-10-30T16:18:43+00:00 4517b5a6c8745f244d89971dc34ec69f5a9eb3d5 Pull clk updates from Stephen Boyd: "Here's the clk changes for the merge window which is dominated in the diffstat by Qualcomm churning out new SoCs that need clk drivers. Looking beyond the sheer amount of lines of mostly data there we have a clk nexus DT binding change in the core clk framework and a driver core patch to add a subsys driver macro. The clock nexus support is useful for devices that map clks internally or for connectors on a board that route clock signals to another board. I suspect the use of this will expand in the future, so we have unit tests to make sure it doesn't break. The driver core change adds subsys_driver() and subsys_platform_driver() so we can register early drivers without open-coding that all (module_platform_driver() is at device initcall level so it isn't be used). Beyond the core framework bits we have lots of changes all over the tree to initialize 'struct clk_init_data'. The potential risk here is that someone forgets to initialize all the members of that structure and either the clk flags cause weird behavior later on or the parents are pointing at junk and the clk is orphaned forever. The patches just initialize the thing with zeroes to be safe. Longer term we should probably move this struct out of 'struct clk_hw' and pass it during clk registration time. That's a much bigger change and would require restructuring entire drivers that rely on the pointer being there. Finally, we have the usual fixes like calculation updates for dividers, handling error paths during clk registration, or fixing clk data now that drivers are using them. Those patches are dwarfed by the amount of new SoC support and only affect those SoCs and the consumers of those clks. Overall I'm more concerned the clk_init_data patches are going to expose some latent bugs that we didn't notice before because something was relying on clks being orphaned and now they're not. Core: - subsys_driver() / subsys_platform_driver() macros - Clock nexus DT binding support (with KUnit tests) - Spread-spectrum configuration validation - Fully initialize struct clk_init_data across many drivers New Drivers: - Anlogic DR1V90 CRU - ZTE zx297520v3 top, matrix, and LSP clocks - Samsung Exynos5515 and ACPM driver extended to Exynos850. - Qualcomm Eliza camera, camera-BIST, GPU, and video clks - Qualcomm Hawi / Maili camera and GPU controllers - Qualcomm Kuno global, RPMh - Qualcomm MSM8952 global, RPM - Qualcomm Nord camera/video clocks, EMAC interconnect, PHY resets - Qualcomm IPQ5210 / IPQ9650 network clocks - i.MX93 350 MHz fractional-N GP-PLL for display - i.MX pll14xx spread-spectrum clock generation - Amlogic A9 SCMI clock controller - Allwinner single-divider "update bit" support - EN7523 Serdes port selection" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (316 commits) clk: imx: pll14xx: support spread spectrum clock generation clk: cdce925: Size the PLL child name buffer for any int clk: stm32: fix clock array size for STM32MP21 dt-bindings: clock: Convert HiSilicon clocks to DT schema clk: lmk04832: Handle reset GPIO lookup errors dt-bindings: clock: anlogic,dr1v90-cru: make external clocks optional clk: tegra: bpmp: remove kcalloc clk: mmp2-audio: add missing PM_CLK dependency clk: zte: Introduce a driver for zx297520v3 LSP clocks clk: zte: Introduce a driver for zx297520v3 matrix clocks clk: zte: Introduce a driver for zx297520v3 top clocks clk: zte: Add zx PLL support infrastructure clk: zte: Add regmap-based clocks clk: zte: Add Clock registration infrastructure dt-bindings: clk: zte: Add zx297520v3 LSP clock and reset controller dt-bindings: clk: zte: Add zx297520v3 matrix clock and reset controller dt-bindings: clk: zte: Add zx297520v3 top clock and reset controller clk: nuvoton: ma35d1: Add missing WDT/WWDT parent clocks dt-bindings: clock: ma35d1: Add missing WDT/WWDT parent clocks dt-bindings: clock: ma35d1: Drop CLK_MAX_IDX define ... 
Pull clk updates from Stephen Boyd:
 "Here's the clk changes for the merge window which is dominated in the
  diffstat by Qualcomm churning out new SoCs that need clk drivers.

  Looking beyond the sheer amount of lines of mostly data there we have
  a clk nexus DT binding change in the core clk framework and a driver
  core patch to add a subsys driver macro.

  The clock nexus support is useful for devices that map clks internally
  or for connectors on a board that route clock signals to another
  board. I suspect the use of this will expand in the future, so we have
  unit tests to make sure it doesn't break.

  The driver core change adds subsys_driver() and
  subsys_platform_driver() so we can register early drivers without
  open-coding that all (module_platform_driver() is at device initcall
  level so it isn't be used).

  Beyond the core framework bits we have lots of changes all over the
  tree to initialize 'struct clk_init_data'. The potential risk here is
  that someone forgets to initialize all the members of that structure
  and either the clk flags cause weird behavior later on or the parents
  are pointing at junk and the clk is orphaned forever. The patches just
  initialize the thing with zeroes to be safe. Longer term we should
  probably move this struct out of 'struct clk_hw' and pass it during
  clk registration time. That's a much bigger change and would require
  restructuring entire drivers that rely on the pointer being there.

  Finally, we have the usual fixes like calculation updates for
  dividers, handling error paths during clk registration, or fixing clk
  data now that drivers are using them. Those patches are dwarfed by the
  amount of new SoC support and only affect those SoCs and the consumers
  of those clks. Overall I'm more concerned the clk_init_data patches
  are going to expose some latent bugs that we didn't notice before
  because something was relying on clks being orphaned and now they're
  not.

  Core:
   - subsys_driver() / subsys_platform_driver() macros
   - Clock nexus DT binding support (with KUnit tests)
   - Spread-spectrum configuration validation
   - Fully initialize struct clk_init_data across many drivers

  New Drivers:
   - Anlogic DR1V90 CRU
   - ZTE zx297520v3 top, matrix, and LSP clocks
   - Samsung Exynos5515 and ACPM driver extended to Exynos850.
   - Qualcomm Eliza camera, camera-BIST, GPU, and video clks
   - Qualcomm Hawi / Maili camera and GPU controllers
   - Qualcomm Kuno global, RPMh
   - Qualcomm MSM8952 global, RPM
   - Qualcomm Nord camera/video clocks, EMAC interconnect, PHY resets
   - Qualcomm IPQ5210 / IPQ9650 network clocks
   - i.MX93 350 MHz fractional-N GP-PLL for display
   - i.MX pll14xx spread-spectrum clock generation
   - Amlogic A9 SCMI clock controller
   - Allwinner single-divider "update bit" support
   - EN7523 Serdes port selection"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (316 commits)
  clk: imx: pll14xx: support spread spectrum clock generation
  clk: cdce925: Size the PLL child name buffer for any int
  clk: stm32: fix clock array size for STM32MP21
  dt-bindings: clock: Convert HiSilicon clocks to DT schema
  clk: lmk04832: Handle reset GPIO lookup errors
  dt-bindings: clock: anlogic,dr1v90-cru: make external clocks optional
  clk: tegra: bpmp: remove kcalloc
  clk: mmp2-audio: add missing PM_CLK dependency
  clk: zte: Introduce a driver for zx297520v3 LSP clocks
  clk: zte: Introduce a driver for zx297520v3 matrix clocks
  clk: zte: Introduce a driver for zx297520v3 top clocks
  clk: zte: Add zx PLL support infrastructure
  clk: zte: Add regmap-based clocks
  clk: zte: Add Clock registration infrastructure
  dt-bindings: clk: zte: Add zx297520v3 LSP clock and reset controller
  dt-bindings: clk: zte: Add zx297520v3 matrix clock and reset controller
  dt-bindings: clk: zte: Add zx297520v3 top clock and reset controller
  clk: nuvoton: ma35d1: Add missing WDT/WWDT parent clocks
  dt-bindings: clock: ma35d1: Add missing WDT/WWDT parent clocks
  dt-bindings: clock: ma35d1: Drop CLK_MAX_IDX define
  ...
Merge branches 'clk-renesas', 'clk-samsung', 'clk-starfive', 'clk-tenstorrent' and 'clk-pile' into clk-next 2026-10-26T23:48:58+00:00 Brian Masney bmasney@redhat.com 2026-10-26T23:48:58+00:00 0d9678b125d8315d62de1261bee67c7e6f21457e * clk-renesas: (25 commits) clk: renesas: r8a78000: Add SGASYNCD8_PERW_BUS clk: renesas: rzg2l: Fix internal clock names clk: renesas: r9a08g046: Add TSU and ADC1 clocks and resets clk: renesas: Add support for RZ/G2M v3.0 clk: renesas: r9a08g046: Add CANFD clocks and resets clk: renesas: r9a08g046: Propagate clk rate for ETH TX mux clocks dt-bindings: clock: Add r8a774a3 CPG Core Clock definitions clk: renesas: r8a779g0: Add ZG clocks clk: renesas: rcar-gen4: Tidy up DEF_GEN4_Z() clk: renesas: r9a09g077: Register SYSC regmap clk: renesas: rcar-gen3: Use FIELD_GET() clk: renesas: rzv2h: Convert to clk_hw based provider API clk: renesas: rzv2h: Drop duplicated parent lookup in fixed_mod_status_clk_register() clk: renesas: r9a08g046: Add PCIe clocks and reset clk: renesas: Make sure clk_init_data is fully initialized clk: renesas: r9a08g046: Add clock and reset entries for LVDS clk: renesas: r9a08g046: Add MIPI DSI and LCDC clock/reset entries clk: renesas: r9a08g046: Sort macro definitions alphabetically clk: renesas: rzg2l: Add support for RZ/G3L DSI mux clk: renesas: rzg2l: Add support for LVDS fixed-factor divider with 4:7 duty cycle ... * clk-samsung: clk: samsung: acpm: add Exynos850 support clk: samsung: acpm: introduce driver data for SoC-specific clocks clk: samsung: Introduce Exynos5515 clock driver clk: samsung: clk-pll: Add support for pll_309 dt-bindings: clock: Add Exynos5515 SoC * clk-starfive: dt-bindings: soc: starfive: Add StarFive JHB100 syscon modules dt-bindings: clock: Add StarFive JHB100 Peripheral-3 clock and reset generator dt-bindings: clock: Add StarFive JHB100 Peripheral-2 clock and reset generator dt-bindings: clock: Add StarFive JHB100 Peripheral-1 clock and reset generator dt-bindings: clock: Add StarFive JHB100 Peripheral-0 clock and reset generator dt-bindings: clock: Add StarFive JHB100 System-2 clock and reset generator dt-bindings: clock: Add StarFive JHB100 System-1 clock and reset generator dt-bindings: clock: Add StarFive JHB100 System-0 clock and reset generator * clk-tenstorrent: MAINTAINERS: Update RISC-V Tenstorrent SoC entry clk: tenstorrent: use regmap_assign_bits() for conditional set/clear clk: tenstorrent: Fix refcount leak on shared gate clk enable failure clk: tenstorrent: Assign .num before accessing .hws * clk-pile: (126 commits) clk: imx: pll14xx: support spread spectrum clock generation clk: cdce925: Size the PLL child name buffer for any int clk: stm32: fix clock array size for STM32MP21 dt-bindings: clock: Convert HiSilicon clocks to DT schema clk: lmk04832: Handle reset GPIO lookup errors dt-bindings: clock: anlogic,dr1v90-cru: make external clocks optional clk: tegra: bpmp: remove kcalloc clk: mmp2-audio: add missing PM_CLK dependency clk: zte: Introduce a driver for zx297520v3 LSP clocks clk: zte: Introduce a driver for zx297520v3 matrix clocks clk: zte: Introduce a driver for zx297520v3 top clocks clk: zte: Add zx PLL support infrastructure clk: zte: Add regmap-based clocks clk: zte: Add Clock registration infrastructure dt-bindings: clk: zte: Add zx297520v3 LSP clock and reset controller dt-bindings: clk: zte: Add zx297520v3 matrix clock and reset controller dt-bindings: clk: zte: Add zx297520v3 top clock and reset controller clk: nuvoton: ma35d1: Add missing WDT/WWDT parent clocks dt-bindings: clock: ma35d1: Add missing WDT/WWDT parent clocks dt-bindings: clock: ma35d1: Drop CLK_MAX_IDX define ... 
* clk-renesas: (25 commits)
  clk: renesas: r8a78000: Add SGASYNCD8_PERW_BUS
  clk: renesas: rzg2l: Fix internal clock names
  clk: renesas: r9a08g046: Add TSU and ADC1 clocks and resets
  clk: renesas: Add support for RZ/G2M v3.0
  clk: renesas: r9a08g046: Add CANFD clocks and resets
  clk: renesas: r9a08g046: Propagate clk rate for ETH TX mux clocks
  dt-bindings: clock: Add r8a774a3 CPG Core Clock definitions
  clk: renesas: r8a779g0: Add ZG clocks
  clk: renesas: rcar-gen4: Tidy up DEF_GEN4_Z()
  clk: renesas: r9a09g077: Register SYSC regmap
  clk: renesas: rcar-gen3: Use FIELD_GET()
  clk: renesas: rzv2h: Convert to clk_hw based provider API
  clk: renesas: rzv2h: Drop duplicated parent lookup in fixed_mod_status_clk_register()
  clk: renesas: r9a08g046: Add PCIe clocks and reset
  clk: renesas: Make sure clk_init_data is fully initialized
  clk: renesas: r9a08g046: Add clock and reset entries for LVDS
  clk: renesas: r9a08g046: Add MIPI DSI and LCDC clock/reset entries
  clk: renesas: r9a08g046: Sort macro definitions alphabetically
  clk: renesas: rzg2l: Add support for RZ/G3L DSI mux
  clk: renesas: rzg2l: Add support for LVDS fixed-factor divider with 4:7 duty cycle
  ...

* clk-samsung:
  clk: samsung: acpm: add Exynos850 support
  clk: samsung: acpm: introduce driver data for SoC-specific clocks
  clk: samsung: Introduce Exynos5515 clock driver
  clk: samsung: clk-pll: Add support for pll_309
  dt-bindings: clock: Add Exynos5515 SoC

* clk-starfive:
  dt-bindings: soc: starfive: Add StarFive JHB100 syscon modules
  dt-bindings: clock: Add StarFive JHB100 Peripheral-3 clock and reset generator
  dt-bindings: clock: Add StarFive JHB100 Peripheral-2 clock and reset generator
  dt-bindings: clock: Add StarFive JHB100 Peripheral-1 clock and reset generator
  dt-bindings: clock: Add StarFive JHB100 Peripheral-0 clock and reset generator
  dt-bindings: clock: Add StarFive JHB100 System-2 clock and reset generator
  dt-bindings: clock: Add StarFive JHB100 System-1 clock and reset generator
  dt-bindings: clock: Add StarFive JHB100 System-0 clock and reset generator

* clk-tenstorrent:
  MAINTAINERS: Update RISC-V Tenstorrent SoC entry
  clk: tenstorrent: use regmap_assign_bits() for conditional set/clear
  clk: tenstorrent: Fix refcount leak on shared gate clk enable failure
  clk: tenstorrent: Assign .num before accessing .hws

* clk-pile: (126 commits)
  clk: imx: pll14xx: support spread spectrum clock generation
  clk: cdce925: Size the PLL child name buffer for any int
  clk: stm32: fix clock array size for STM32MP21
  dt-bindings: clock: Convert HiSilicon clocks to DT schema
  clk: lmk04832: Handle reset GPIO lookup errors
  dt-bindings: clock: anlogic,dr1v90-cru: make external clocks optional
  clk: tegra: bpmp: remove kcalloc
  clk: mmp2-audio: add missing PM_CLK dependency
  clk: zte: Introduce a driver for zx297520v3 LSP clocks
  clk: zte: Introduce a driver for zx297520v3 matrix clocks
  clk: zte: Introduce a driver for zx297520v3 top clocks
  clk: zte: Add zx PLL support infrastructure
  clk: zte: Add regmap-based clocks
  clk: zte: Add Clock registration infrastructure
  dt-bindings: clk: zte: Add zx297520v3 LSP clock and reset controller
  dt-bindings: clk: zte: Add zx297520v3 matrix clock and reset controller
  dt-bindings: clk: zte: Add zx297520v3 top clock and reset controller
  clk: nuvoton: ma35d1: Add missing WDT/WWDT parent clocks
  dt-bindings: clock: ma35d1: Add missing WDT/WWDT parent clocks
  dt-bindings: clock: ma35d1: Drop CLK_MAX_IDX define
  ...
dt-bindings: clk: zte: Add zx297520v3 LSP clock and reset controller 2026-10-26T23:45:49+00:00 Stefan Dösinger stefandoesinger@gmail.com 2026-09-27T20:13:31+00:00 244539a22fbd11e18dbcbc02453e0f07f1a6368c The clock controller of the zx297520v3 Low Speed Peripherals is relatively clean. One register per device with gates, muxes and resets and for some devices a divider. There are even bits in the matrix controller to control propagation of clock lines down to LSP. The clocks are sorted by register address and I am convinced that the device list is complete. There are, however, a few more registers that are likely extra dividers for TDM and I2S devices. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Stefan Dösinger <stefandoesinger@gmail.com> Signed-off-by: Brian Masney <bmasney@redhat.com> 
The clock controller of the zx297520v3 Low Speed Peripherals is
relatively clean. One register per device with gates, muxes and resets
and for some devices a divider. There are even bits in the matrix
controller to control propagation of clock lines down to LSP.

The clocks are sorted by register address and I am convinced that the
device list is complete. There are, however, a few more registers that
are likely extra dividers for TDM and I2S devices.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Stefan Dösinger <stefandoesinger@gmail.com>
Signed-off-by: Brian Masney <bmasney@redhat.com>
dt-bindings: clk: zte: Add zx297520v3 matrix clock and reset controller 2026-10-26T23:45:49+00:00 Stefan Dösinger stefandoesinger@gmail.com 2026-09-27T20:50:55+00:00 574e62ac2dd913774486b09ff2672be872f23aed This controller contains clocks and resets for high speed devices on the zx297520v3 board and hardware spinlocks that I expect will be necessary to communicate correctly with the LTE DSP firmware blob. I don't know much about the hwlocks yet other than that they exist, so there is no header yet adding meaning to their indices. Presumably that meaning doesn't exist in hardware and is de facto defined by ZTE's firmware blobs running on the rprocs. The zte-zx297520v3-crm driver will instantiate separate MFD children for clocks and resets, which are handled by separate clock and reset drivers. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Stefan Dösinger <stefandoesinger@gmail.com> Signed-off-by: Brian Masney <bmasney@redhat.com> 
This controller contains clocks and resets for high speed devices on the
zx297520v3 board and hardware spinlocks that I expect will be necessary
to communicate correctly with the LTE DSP firmware blob.

I don't know much about the hwlocks yet other than that they exist, so
there is no header yet adding meaning to their indices. Presumably that
meaning doesn't exist in hardware and is de facto defined by ZTE's
firmware blobs running on the rprocs.

The zte-zx297520v3-crm driver will instantiate separate MFD children for
clocks and resets, which are handled by separate clock and reset
drivers.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Stefan Dösinger <stefandoesinger@gmail.com>
Signed-off-by: Brian Masney <bmasney@redhat.com>
dt-bindings: clk: zte: Add zx297520v3 top clock and reset controller 2026-10-26T23:45:49+00:00 Stefan Dösinger stefandoesinger@gmail.com 2026-09-27T20:13:29+00:00 7bdc3c32d5037f9d55c5f109e29f0c2c066ba522 These SoCs have 3 clock and reset controllers: Top, Matrix and LSP. Clocks go from oscillator -> top -> matrix -> LSP, with a register in top controlling most clocks that get passed to matrix and a register in matrix controlling all the clocks that get passed to LSP. Generally every device has two clocks (one work clock, and one that connects it to the bus, I call it PCLK), two reset bits (I don't know what the difference is - sometimes asserting one is enough to reset the device, sometimes both need to be asserted). PCLK and WCLK are controlled by individual gates. Some devices have a mux and/or a divider for their work clock. Some devices, like the GPIO controller, only have reset bits and no clocks. The top clock controller is fed by a 26 MHz external oscillator and has 4 PLLs to generate other clock rates. ZTE's kernel mostly relies on the boot ROM to set up PLLs, but one LTE-related PLL is not configured on some boards. Therefore my driver contains code to program PLLs. It produces identical settings as the boot ROM for the pre-programmed frequencies. Not all clocks will have an explicit user in the end. I am defining a lot of them simply to shut them off. The boot loader sets up a few of the proprietary timers, which will send regular IRQs (although the kernel of course doesn't need to listen to them). I don't plan to add a driver for the proprietary timer as I see no use for them - the ARM arch timer works just fine. I will add a driver for the very similar proprietary watchdog though. The clock list in this patch is pretty complete but not exhaustive. There are other bits that are enabled, but I couldn't deduce what they are controlling by trial and error. Some of them seem to do nothing. Others cause an instant hang of the board when disabled. It is quite likely that a handful more clocks will be added in the future, but not a large number. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Stefan Dösinger <stefandoesinger@gmail.com> Signed-off-by: Brian Masney <bmasney@redhat.com> 
These SoCs have 3 clock and reset controllers: Top, Matrix and LSP.
Clocks go from oscillator -> top -> matrix -> LSP, with a register in
top controlling most clocks that get passed to matrix and a register in
matrix controlling all the clocks that get passed to LSP.

Generally every device has two clocks (one work clock, and one that
connects it to the bus, I call it PCLK), two reset bits (I don't know
what the difference is - sometimes asserting one is enough to reset the
device, sometimes both need to be asserted). PCLK and WCLK are
controlled by individual gates. Some devices have a mux and/or a
divider for their work clock. Some devices, like the GPIO controller,
only have reset bits and no clocks.

The top clock controller is fed by a 26 MHz external oscillator and has 4
PLLs to generate other clock rates. ZTE's kernel mostly relies on the
boot ROM to set up PLLs, but one LTE-related PLL is not configured
on some boards. Therefore my driver contains code to program PLLs. It
produces identical settings as the boot ROM for the pre-programmed
frequencies.

Not all clocks will have an explicit user in the end. I am defining a
lot of them simply to shut them off. The boot loader sets up a few of
the proprietary timers, which will send regular IRQs (although the
kernel of course doesn't need to listen to them). I don't plan to add a
driver for the proprietary timer as I see no use for them - the ARM arch
timer works just fine. I will add a driver for the very similar
proprietary watchdog though.

The clock list in this patch is pretty complete but not exhaustive.
There are other bits that are enabled, but I couldn't deduce what they
are controlling by trial and error. Some of them seem to do nothing.
Others cause an instant hang of the board when disabled. It is quite
likely that a handful more clocks will be added in the future, but not a
large number.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Stefan Dösinger <stefandoesinger@gmail.com>
Signed-off-by: Brian Masney <bmasney@redhat.com>
Merge tag 'soc-drivers-7.4' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc 2026-10-22T17:52:50+00:00 Linus Torvalds torvalds@linux-foundation.org 2026-10-22T17:52:50+00:00 2e51c645fee243dbcb5cee3eb063b5713317444c Pull SoC driver updates from Arnd Bergmann: "There are lots of minor updates for driver subsystems managed through the soc tree (turris-omnia platform, cache driver, tee drivers, arm-cci, bus, memory) as well as soc vendor specific drivers (starfive, xilinx, microchip, nxp, amlogic, imx, renesas, samsung, ti, nvidia). The more notable changes are: - Larger updates for Qualcomm SoCs including support for SM8950 (Maili) SM8975 (Hawi), Glymur, Shikra, and IPQ5424 - Added SoC support for Exynos5515, Tegra264, Tegra410, R8A774A3, and MT8167 in existing drivers - Arm SCMI firmware driver support for ACPI PCC transport and module autoloading of protocol specific drivers - Apple crash log support for CrgA embedded controller" * tag 'soc-drivers-7.4' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (176 commits) platform: cznic: turris-omnia-mcu: stop button emulation producers cache: Make cpu_cache_invalidate_memregion() error out if there are no handlers soc: mpfs: use kref cleanup on probe failure arm64: enable HAVE_SHARED_GPIOS for all ARM64 platforms bus: arm-cci: Drop cci-control-port node reference in __cci_ace_get_port() bus: arm-cci: Drop CPU node reference in cci_ace_init_ports() soc: fsl: dpio: Free the IRQ before releasing the I/O object soc: fsl: dpio: Fix cleanup on IRQ registration failure bus: fsl-mc: Annotate fsl_mc_io.portal_virt_addr with __counted_by_ptr bus: fsl-mc: drop the fwnode links of the dpmacs nodes soc: fsl: cpm1: tsa: Fix clock leak in tsa_of_parse_tdms() soc: qcom: geni-se: Drop unused icc_ddr parameter from geni_icc_get() firmware: qcom: scm: Allow QSEECOM on ThinkPad T14s Gen 7 dt-bindings: mailbox: qcom: Document Maili CPUCP mailbox controller dt-bindings: spmi: glymur-spmi-pmic-arb: Add compatible for Qualcomm Maili SoC soc: qcom: pmic_pdcharger_ulog: prevent work requeue during remove ASoC: dt-bindings: qcom,apr: Add modem_apps GLINK channel for shikra firmware: qcom: tzmem: disable SHM bridge for SM7125 platform soc: qcom: ubwc: Add Kalambo UBWC config firmware: qcom: scm: Allow QSEECOM on Kalambo CRD ... 
Pull SoC driver updates from Arnd Bergmann:
 "There are lots of minor updates for driver subsystems managed through
  the soc tree (turris-omnia platform, cache driver, tee drivers,
  arm-cci, bus, memory) as well as soc vendor specific drivers
  (starfive, xilinx, microchip, nxp, amlogic, imx, renesas, samsung, ti,
  nvidia).

  The more notable changes are:

   - Larger updates for Qualcomm SoCs including support for SM8950
     (Maili) SM8975 (Hawi), Glymur, Shikra, and IPQ5424

   - Added SoC support for Exynos5515, Tegra264, Tegra410, R8A774A3, and
     MT8167 in existing drivers

   - Arm SCMI firmware driver support for ACPI PCC transport and module
     autoloading of protocol specific drivers

   - Apple crash log support for CrgA embedded controller"

* tag 'soc-drivers-7.4' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (176 commits)
  platform: cznic: turris-omnia-mcu: stop button emulation producers
  cache: Make cpu_cache_invalidate_memregion() error out if there are no handlers
  soc: mpfs: use kref cleanup on probe failure
  arm64: enable HAVE_SHARED_GPIOS for all ARM64 platforms
  bus: arm-cci: Drop cci-control-port node reference in __cci_ace_get_port()
  bus: arm-cci: Drop CPU node reference in cci_ace_init_ports()
  soc: fsl: dpio: Free the IRQ before releasing the I/O object
  soc: fsl: dpio: Fix cleanup on IRQ registration failure
  bus: fsl-mc: Annotate fsl_mc_io.portal_virt_addr with __counted_by_ptr
  bus: fsl-mc: drop the fwnode links of the dpmacs nodes
  soc: fsl: cpm1: tsa: Fix clock leak in tsa_of_parse_tdms()
  soc: qcom: geni-se: Drop unused icc_ddr parameter from geni_icc_get()
  firmware: qcom: scm: Allow QSEECOM on ThinkPad T14s Gen 7
  dt-bindings: mailbox: qcom: Document Maili CPUCP mailbox controller
  dt-bindings: spmi: glymur-spmi-pmic-arb: Add compatible for Qualcomm Maili SoC
  soc: qcom: pmic_pdcharger_ulog: prevent work requeue during remove
  ASoC: dt-bindings: qcom,apr: Add modem_apps GLINK channel for shikra
  firmware: qcom: tzmem: disable SHM bridge for SM7125 platform
  soc: qcom: ubwc: Add Kalambo UBWC config
  firmware: qcom: scm: Allow QSEECOM on Kalambo CRD
  ...
dt-bindings: soc: starfive: Add StarFive JHB100 syscon modules 2026-10-02T20:17:31+00:00 Changhuang Liang changhuang.liang@starfivetech.com 2026-08-28T09:56:01+00:00 c4a545d3e428e9600d670fa8a08098b7bc82d5ec Add documentation to describe StarFive JHB100 SoC System Controller Registers. Add the PLL clocks for the sys0, per0, and per1 domains under syscon, as well as the PCIe RP reset. Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> 
Add documentation to describe StarFive JHB100 SoC System Controller
Registers.

Add the PLL clocks for the sys0, per0, and per1 domains under syscon,
as well as the PCIe RP reset.

Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
dt-bindings: clock: Add StarFive JHB100 Peripheral-3 clock and reset generator 2026-10-02T19:58:09+00:00 Changhuang Liang changhuang.liang@starfivetech.com 2026-09-30T12:43:13+00:00 17986e31f3b6142c302c8f9af16540422787daf9 Add bindings for the Peripheral-3 clock and reset generator (PER3CRG) on the JHB100 RISC-V SoC by StarFive Ltd. Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> 
Add bindings for the Peripheral-3 clock and reset generator (PER3CRG)
on the JHB100 RISC-V SoC by StarFive Ltd.

Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
dt-bindings: clock: Add StarFive JHB100 Peripheral-2 clock and reset generator 2026-10-02T19:58:09+00:00 Changhuang Liang changhuang.liang@starfivetech.com 2026-09-30T12:43:11+00:00 5b86a2f9415fdf4ef1188fdfe0dafb1727328cfd Add bindings for the Peripheral-2 clock and reset generator (PER2CRG) on the JHB100 RISC-V SoC by StarFive Ltd. Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> 
Add bindings for the Peripheral-2 clock and reset generator (PER2CRG)
on the JHB100 RISC-V SoC by StarFive Ltd.

Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
dt-bindings: clock: Add StarFive JHB100 Peripheral-1 clock and reset generator 2026-10-02T19:58:09+00:00 Changhuang Liang changhuang.liang@starfivetech.com 2026-09-30T12:43:09+00:00 d20c33354c2234f52f426d283eaf85b1e4f375dd Add bindings for the Peripheral-1 clock and reset generator (PER1CRG) on the JHB100 RISC-V SoC by StarFive Ltd. Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> 
Add bindings for the Peripheral-1 clock and reset generator (PER1CRG)
on the JHB100 RISC-V SoC by StarFive Ltd.

Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>