Pull clk updates from Stephen Boyd:
"Here's the pile of clk driver patches. The usual suspects^Wsilicon
vendors are all here, adding new SoC support and fixing existing code.
There are a few patches to the clk framework here as well. They've
been baking in linux-next for weeks so I'm hoping we don't have to
revert them. The disable OF node patch is probably the scariest one
although it seems unlikely that a system would be relying on a driver
_not_ probing because the clk never appeared, but you never know.
Nothing looks out of the ordinary on the driver side but that's
because it's mostly a bunch of data.
Core:
- Use dev_err_probe() in the clk registration path (Peering into the
crystal ball shows many patches that remove printks)
- Check for disabled OF nodes in of_clk_get_hw_from_clkspec()
New Drivers:
- Allwinner A523/T527 clk driver
- Qualcomm IPQ9574 NSS clk driver
- Qualcomm QCS8300 GPU and video clk drivers
- Qualcomm SDM429 RPM clks
- Qualcomm QCM6490 LPASS (low power audio) resets
- Samsung Exynos2200: driver for several clock controllers (Alive,
CMGP, HSI, PERIC/PERIS, TOP, UFS and VFS)
- Samsung Exynos7870: Driver for several clock controllers (Alive,
MIF, DISP AUD, FSYS, G3D, ISP, MFC and PERI)
- Rockchip rk3528 and rk3562 clk driver
Updates:
- Various fixes to SoC clk drivers for incorrect data, avoid touching
protected registers, etc.
- Additions for some missing clks in existing SoC clk drivers
- DT schema conversions from text to YAML
- Kconfig cleanups to allow drivers to be compiled on moar
architectures"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (125 commits)
clk: qcom: Add NSS clock Controller driver for IPQ9574
clk: qcom: gcc-ipq9574: Add support for gpll0_out_aux clock
dt-bindings: clock: Add ipq9574 NSSCC clock and reset definitions
dt-bindings: clock: gcc-ipq9574: Add definition for GPLL0_OUT_AUX
clk: qcom: gcc-msm8953: fix stuck venus0_core0 clock
clk: qcom: mmcc-sdm660: fix stuck video_subcore0 clock
dt-bindings: clock: qcom,x1e80100-camcc: Fix the list of required-opps
clk: amlogic: a1: fix a typo
clk: amlogic: gxbb: drop non existing 32k clock parent
clk: amlogic: gxbb: drop incorrect flag on 32k clock
clk: amlogic: g12b: fix cluster A parent data
clk: amlogic: g12a: fix mmc A peripheral clock
dt-bindings: clocks: atmel,at91rm9200-pmc: add missing compatibles
dt-bindings: reset: fix double id on rk3562-cru reset ids
drivers: clk: qcom: ipq5424: fix the freq table of sdcc1_apps clock
clk: qcom: lpassaudiocc-sc7280: Add support for LPASS resets for QCM6490
dt-bindings: clock: qcom: Add compatible for QCM6490 boards
clk: qcom: gdsc: Update the status poll timeout for GDSC
clk: qcom: gdsc: Set retain_ff before moving to HW CTRL
clk: davinci: remove support for da830
...
Pull remoteproc updates from Bjorn Andersson: - Transition the i.MX8MP DSP remoteproc driver to use the reset framework for driving the run/stall reset bits - Add support for managing the modem remoteprocessor on the Qualcomm MSM8226, MSM8926, and SM8750 platforms * tag 'rproc-v6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/remoteproc/linux: (28 commits) remoteproc: qcom_q6v5_pas: Make single-PD handling more robust remoteproc: qcom_q6v5_pas: Use resource with CX PD for MSM8226 remoteproc: core: Clear table_sz when rproc_shutdown remoteproc: sysmon: Update qcom_add_sysmon_subdev() comment dt-bindings: remoteproc: Consolidate SC8180X and SM8150 PAS files irqdomain: remoteproc: Switch to of_fwnode_handle() remoteproc: qcom: pas: add minidump_id to SC7280 WPSS remoteproc: imx_dsp_rproc: Document run_stall struct member remoteproc: qcom: pas: Add SM8750 MPSS dt-bindings: remoteproc: Add SM8750 MPSS imx_dsp_rproc: Use reset controller API to control the DSP reset: imx8mp-audiomix: Add support for DSP run/stall reset: imx8mp-audiomix: Introduce active_low configuration option reset: imx8mp-audiomix: Prepare the code for more reset bits reset: imx8mp-audiomix: Add prefix for internal macro dt-bindings: dsp: fsl,dsp: Add resets property dt-bindings: reset: audiomix: Add reset ids for EARC and DSP remoteproc: qcom_wcnss: Handle platforms with only single power domain dt-bindings: remoteproc: qcom,wcnss-pil: Add support for single power-domain platforms remoteproc: qcom_q6v5_mss: Add modem support on MSM8926 ...
Pull crypto updates from Herbert Xu: "API: - Remove legacy compression interface - Improve scatterwalk API - Add request chaining to ahash and acomp - Add virtual address support to ahash and acomp - Add folio support to acomp - Remove NULL dst support from acomp Algorithms: - Library options are fuly hidden (selected by kernel users only) - Add Kerberos5 algorithms - Add VAES-based ctr(aes) on x86 - Ensure LZO respects output buffer length on compression - Remove obsolete SIMD fallback code path from arm/ghash-ce Drivers: - Add support for PCI device 0x1134 in ccp - Add support for rk3588's standalone TRNG in rockchip - Add Inside Secure SafeXcel EIP-93 crypto engine support in eip93 - Fix bugs in tegra uncovered by multi-threaded self-test - Fix corner cases in hisilicon/sec2 Others: - Add SG_MITER_LOCAL to sg miter - Convert ubifs, hibernate and xfrm_ipcomp from legacy API to acomp" * tag 'v6.15-p1' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: (187 commits) crypto: testmgr - Add multibuffer acomp testing crypto: acomp - Fix synchronous acomp chaining fallback crypto: testmgr - Add multibuffer hash testing crypto: hash - Fix synchronous ahash chaining fallback crypto: arm/ghash-ce - Remove SIMD fallback code path crypto: essiv - Replace memcpy() + NUL-termination with strscpy() crypto: api - Call crypto_alg_put in crypto_unregister_alg crypto: scompress - Fix incorrect stream freeing crypto: lib/chacha - remove unused arch-specific init support crypto: remove obsolete 'comp' compression API crypto: compress_null - drop obsolete 'comp' implementation crypto: cavium/zip - drop obsolete 'comp' implementation crypto: zstd - drop obsolete 'comp' implementation crypto: lzo - drop obsolete 'comp' implementation crypto: lzo-rle - drop obsolete 'comp' implementation crypto: lz4hc - drop obsolete 'comp' implementation crypto: lz4 - drop obsolete 'comp' implementation crypto: deflate - drop obsolete 'comp' implementation crypto: 842 - drop obsolete 'comp' implementation crypto: nx - Migrate to scomp API ...
* clk-allwinner: clk: sunxi-ng: add support for the A523/T527 PRCM CCU clk: sunxi-ng: a523: add reset lines clk: sunxi-ng: a523: add bus clock gates clk: sunxi-ng: a523: remaining mod clocks clk: sunxi-ng: a523: add USB mod clocks clk: sunxi-ng: a523: add interface mod clocks clk: sunxi-ng: a523: add system mod clocks clk: sunxi-ng: a523: add video mod clocks clk: sunxi-ng: a523: Add support for bus clocks clk: sunxi-ng: Add support for the A523/T527 CCU PLLs dt-bindings: clk: sunxi-ng: document two Allwinner A523 CCUs clk: sunxi-ng: Add support for update bit clk: sunxi-ng: mp: provide wrappers for setting feature flags clk: sunxi-ng: mp: introduce dual-divider clock clk: sunxi-ng: h616: Reparent GPU clock during frequency changes clk: sunxi-ng: h616: Add clock/reset for LCD TCON dt-bindings: clock: sun50i-h616-ccu: Add LCD TCON clk and reset * clk-amlogic: clk: amlogic: a1: fix a typo clk: amlogic: gxbb: drop non existing 32k clock parent clk: amlogic: gxbb: drop incorrect flag on 32k clock clk: amlogic: g12b: fix cluster A parent data clk: amlogic: g12a: fix mmc A peripheral clock * clk-qcom: (41 commits) clk: qcom: Add NSS clock Controller driver for IPQ9574 clk: qcom: gcc-ipq9574: Add support for gpll0_out_aux clock dt-bindings: clock: Add ipq9574 NSSCC clock and reset definitions dt-bindings: clock: gcc-ipq9574: Add definition for GPLL0_OUT_AUX clk: qcom: gcc-msm8953: fix stuck venus0_core0 clock clk: qcom: mmcc-sdm660: fix stuck video_subcore0 clock dt-bindings: clock: qcom,x1e80100-camcc: Fix the list of required-opps drivers: clk: qcom: ipq5424: fix the freq table of sdcc1_apps clock clk: qcom: lpassaudiocc-sc7280: Add support for LPASS resets for QCM6490 dt-bindings: clock: qcom: Add compatible for QCM6490 boards clk: qcom: gdsc: Update the status poll timeout for GDSC clk: qcom: gdsc: Set retain_ff before moving to HW CTRL clk: qcom: gcc-sm8650: Do not turn off USB GDSCs during gdsc_disable() clk: qcom: videocc: Constify 'struct qcom_cc_desc' clk: qcom: gpucc: Constify 'struct qcom_cc_desc' clk: qcom: dispcc: Constify 'struct qcom_cc_desc' clk: qcom: camcc: Constify 'struct qcom_cc_desc' dt-bindings: clock: qcom: sm8450-camcc: Remove qcom,x1e80100-camcc leftover clk: qcom: Add support for Video Clock Controller on QCS8300 clk: qcom: Add support for GPU Clock Controller on QCS8300 ...
Add NSSCC clock and reset definitions for ipq9574. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com> Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com> Link: https://lore.kernel.org/r/20250313110359.242491-4-quic_mmanikan@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Id 173 was accidentially used two times for SRST_P_DDR_HWLP and
SRST_P_DDR_PHY. This makes both resets ambiguous and also causes build
warnings like:
drivers/clk/rockchip/rst-rk3562.c:21:57: error: initialized field overwritten [-Werror=override-init]
21 | #define RK3562_DDRCRU_RESET_OFFSET(id, reg, bit) [id] = (0x20000*4 + reg * 16 + bit)
| ^
drivers/clk/rockchip/rst-rk3562.c:266:9: note: in expansion of macro 'RK3562_DDRCRU_RESET_OFFSET'
266 | RK3562_DDRCRU_RESET_OFFSET(SRST_P_DDR_PHY, 0, 8),
| ^~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/clk/rockchip/rst-rk3562.c:21:57: note: (near initialization for 'rk3562_register_offset[173]')
21 | #define RK3562_DDRCRU_RESET_OFFSET(id, reg, bit) [id] = (0x20000*4 + reg * 16 + bit)
| ^
drivers/clk/rockchip/rst-rk3562.c:266:9: note: in expansion of macro 'RK3562_DDRCRU_RESET_OFFSET'
266 | RK3562_DDRCRU_RESET_OFFSET(SRST_P_DDR_PHY, 0, 8),
| ^~~~~~~~~~~~~~~~~~~~~~~~~~
To fix that issue give SRST_P_DDR_PHY a new and now unique id.
Reported-by: Stephen Boyd <sboyd@kernel.org>
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202503121743.0zcDf6nE-lkp@intel.com/
Fixes: dd113c4fefc8 ("dt-bindings: clock: Add RK3562 cru")
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20250312215923.275625-1-heiko@sntech.de
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add reset ids used for EARC and DSP on i.MX8MP platform. Acked-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20250311085812.1296243-2-daniel.baluta@nxp.com Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
The Allwinner A523/T527 SoCs have four CCUs, this adds the binding for the main and the PRCM R-CCU. The source clock list differs in some annoying details, and folding this into the existing Allwinner CCU clock binding document gets quite unwieldy, so create a new document for these CCUs. Add the new compatible string, along with the required input clock lists. This conditionally describes the input clock lists, to make adding support for the other two CCUs easier. Also add the DT binding headers, listing all the clocks with their ID numbers. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20250307002628.10684-5-andre.przywara@arm.com Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Document the device tree bindings of the rockchip rk3562 SoC clock and reset unit. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: "Rob Herring (Arm)" <robh@kernel.org> Link: https://lore.kernel.org/r/20250227105916.2340856-2-kever.yang@rock-chips.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
There are two types of clocks in RK3528 SoC, CRU-managed and SCMI-managed. Independent IDs are assigned to them. For the reset part, differing from previous Rockchip SoCs and downstream bindings which embeds register offsets into the IDs, gapless numbers starting from zero are used. Signed-off-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250217061142.38480-6-ziyao@disroot.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>