linux-toradex.git/include/kvm, branch v4.11-rc3

KVM: arm/arm64: Emulate the EL1 phys timer registers

2017-02-08T15:13:37+00:00

Emulate read and write operations to CNTP_TVAL, CNTP_CVAL and CNTP_CTL.
Now VMs are able to use the EL1 physical timer.

Signed-off-by: Jintack Lim 
Reviewed-by: Christoffer Dall 
Signed-off-by: Marc Zyngier

KVM: arm/arm64: Initialize the emulated EL1 physical timer

2017-02-08T15:13:34+00:00

Initialize the emulated EL1 physical timer with the default irq number.

Signed-off-by: Jintack Lim 
Reviewed-by: Christoffer Dall 
Signed-off-by: Marc Zyngier

KVM: arm/arm64: Add the EL1 physical timer context

2017-02-08T15:13:34+00:00

Add the EL1 physical timer context.

Signed-off-by: Jintack Lim 
Acked-by: Christoffer Dall 
Signed-off-by: Marc Zyngier

KVM: arm/arm64: Decouple kvm timer functions from virtual timer

2017-02-08T15:13:33+00:00

Now that we have a separate structure for timer context, make functions
generic so that they can work with any timer context, not just the
virtual timer context.  This does not change the virtual timer
functionality.

Signed-off-by: Jintack Lim 
Acked-by: Marc Zyngier 
Acked-by: Christoffer Dall 
Signed-off-by: Marc Zyngier

KVM: arm/arm64: Move cntvoff to each timer context

2017-02-08T15:13:33+00:00

Make cntvoff per each timer context. This is helpful to abstract kvm
timer functions to work with timer context without considering timer
types (e.g. physical timer or virtual timer).

This also would pave the way for ever doing adjustments of the cntvoff
on a per-CPU basis if that should ever make sense.

Signed-off-by: Jintack Lim 
Signed-off-by: Christoffer Dall 
Signed-off-by: Marc Zyngier

KVM: arm/arm64: Abstract virtual timer context into separate structure

2017-02-08T15:13:32+00:00

Abstract virtual timer context into a separate structure and change all
callers referring to timer registers, irq state and so on. No change in
functionality.

This is about to become very handy when adding the EL1 physical timer.

Signed-off-by: Jintack Lim 
Acked-by: Christoffer Dall 
Acked-by: Marc Zyngier 
Signed-off-by: Marc Zyngier

KVM: arm/arm64: vgic: Implement VGICv3 CPU interface access

2017-01-30T13:47:25+00:00

VGICv3 CPU interface registers are accessed using
KVM_DEV_ARM_VGIC_CPU_SYSREGS ioctl. These registers are accessed
as 64-bit. The cpu MPIDR value is passed along with register id.
It is used to identify the cpu for registers access.

The VM that supports SEIs expect it on destination machine to handle
guest aborts and hence checked for ICC_CTLR_EL1.SEIS compatibility.
Similarly, VM that supports Affinity Level 3 that is required for AArch64
mode, is required to be supported on destination machine. Hence checked
for ICC_CTLR_EL1.A3V compatibility.

The arch/arm64/kvm/vgic-sys-reg-v3.c handles read and write of VGIC
CPU registers for AArch64.

For AArch32 mode, arch/arm/kvm/vgic-v3-coproc.c file is created but
APIs are not implemented.

Updated arch/arm/include/uapi/asm/kvm.h with new definitions
required to compile for AArch32.

The version of VGIC v3 specification is defined here
Documentation/virtual/kvm/devices/arm-vgic-v3.txt

Acked-by: Christoffer Dall 
Reviewed-by: Eric Auger 
Signed-off-by: Pavel Fedin 
Signed-off-by: Vijaya Kumar K 
Signed-off-by: Marc Zyngier

KVM: arm/arm64: vgic: Add debugfs vgic-state file

2017-01-25T12:50:03+00:00

Add a file to debugfs to read the in-kernel state of the vgic.  We don't
do any locking of the entire VGIC state while traversing all the IRQs,
so if the VM is running the user/developer may not see a quiesced state,
but should take care to pause the VM using facilities in user space for
that purpose.

We also don't support LPIs yet, but they can be added easily if needed.

Reviewed-by: Eric Auger 
Tested-by: Eric Auger 
Tested-by: Andre Przywara 
Acked-by: Marc Zyngier 
Signed-off-by: Christoffer Dall

KVM: arm/arm64: Remove struct vgic_irq pending field

2017-01-25T12:26:13+00:00

One of the goals behind the VGIC redesign was to get rid of cached or
intermediate state in the data structures, but we decided to allow
ourselves to precompute the pending value of an IRQ based on the line
level and pending latch state.  However, this has now become difficult
to base proper GICv3 save/restore on, because there is a potential to
modify the pending state without knowing if an interrupt is edge or
level configured.

See the following post and related message for more background:
https://lists.cs.columbia.edu/pipermail/kvmarm/2017-January/023195.html

This commit gets rid of the precomputed pending field in favor of a
function that calculates the value when needed, irq_is_pending().

The soft_pending field is renamed to pending_latch to represent that
this latch is the equivalent hardware latch which gets manipulated by
the input signal for edge-triggered interrupts and when writing to the
SPENDR/CPENDR registers.

After this commit save/restore code should be able to simply restore the
pending_latch state, line_level state, and config state in any order and
get the desired result.

Reviewed-by: Andre Przywara 
Reviewed-by: Marc Zyngier 
Tested-by: Andre Przywara 
Signed-off-by: Christoffer Dall

KVM: arm64: Access CNTHCTL_EL2 bit fields correctly on VHE systems

2017-01-13T11:19:25+00:00

Current KVM world switch code is unintentionally setting wrong bits to
CNTHCTL_EL2 when E2H == 1, which may allow guest OS to access physical
timer.  Bit positions of CNTHCTL_EL2 are changing depending on
HCR_EL2.E2H bit.  EL1PCEN and EL1PCTEN are 1st and 0th bits when E2H is
not set, but they are 11th and 10th bits respectively when E2H is set.

In fact, on VHE we only need to set those bits once, not for every world
switch. This is because the host kernel runs in EL2 with HCR_EL2.TGE ==
1, which makes those bits have no effect for the host kernel execution.
So we just set those bits once for guests, and that's it.

Signed-off-by: Jintack Lim 
Reviewed-by: Marc Zyngier 
Signed-off-by: Marc Zyngier