linux-toradex.git/include/linux/clk-provider.h, branch v3.19.7

clk: Change clk_ops->determine_rate to return a clk_hw as the best parent

2014-12-04T00:21:37+00:00

This is in preparation for clock providers to not have to deal with struct clk.

Signed-off-by: Tomeu Vizoso 
Reviewed-by: Stephen Boyd 
Signed-off-by: Michael Turquette

clk: change clk_debugfs_add_file to take a struct clk_hw

2014-12-03T23:15:35+00:00

Instead of struct clk, as this should be only used by providers.

Signed-off-by: Tomeu Vizoso 
Reviewed-by: Stephen Boyd 
Signed-off-by: Michael Turquette

clk: Don't expose __clk_get_accuracy

2014-12-03T23:15:34+00:00

As it's only used internally, in drivers/clk/clk.c.

Signed-off-by: Tomeu Vizoso 
Reviewed-by: Stephen Boyd 
Signed-off-by: Michael Turquette

clk: Remove unused function __clk_get_prepare_count

2014-12-03T23:15:34+00:00

Signed-off-by: Tomeu Vizoso 
Reviewed-by: Stephen Boyd 
Signed-off-by: Michael Turquette

clk-divider: Fix READ_ONLY when divider > 1

2014-11-17T19:13:52+00:00

Commit 79c6ab509558 (clk: divider: add CLK_DIVIDER_READ_ONLY flag) in
v3.16 introduced the CLK_DIVIDER_READ_ONLY flag which caused the
recalc_rate() and round_rate() clock callbacks to be omitted.

However using this flag has the unfortunate side effect of causing the
clock recalculation code when a clock rate change is attempted to always
treat it as a pass-through clock, i.e. with a fixed divide of 1, which
may not be the case. Child clock rates are then recalculated using the
wrong parent rate.

Therefore instead of dropping the recalc_rate() and round_rate()
callbacks, alter clk_divider_bestdiv() to always report the current
divider as the best divider so that it is never altered.

For me the read only clock was the system clock, which divided the PLL
rate by 2, from which both the UART and the SPI clocks were divided.
Initial setting of the UART rate set it correctly, but when the SPI
clock was set, the other child clocks were miscalculated. The UART clock
was recalculated using the PLL rate as the parent rate, resulting in a
UART new_rate of double what it should be, and a UART which spewed forth
garbage when the rate changes were propagated.

Signed-off-by: James Hogan 
Cc: Thomas Abraham 
Cc: Tomasz Figa 
Cc: Max Schwarz 
Cc:  # v3.16+
Acked-by: Haojian Zhuang 
Signed-off-by: Michael Turquette

Merge tag 'sunxi-clocks-for-3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next

2014-09-27T19:52:33+00:00

Allwinner Clocks Additions for 3.18

The most important part of this serie is the addition of the phase API to
handle the MMC clocks in the Allwinner SoCs.

Apart from that, the A23 gained a new mbus driver, and there's a fix for a
incorrect divider table on the APB0 clock.

clk: Add a function to retrieve phase

2014-09-27T06:57:51+00:00

The current phase API doesn't look into the actual hardware to get the phase
value, but will rather get it from a variable only set by the set_phase
function.

This will cause issue when the client driver will never call the set_phase
function, where we can end up having a reported phase that will not match what
the hardware has been programmed to by the bootloader or what phase is
programmed out of reset.

Add a new get_phase function for the drivers to implement so that we can get
this value.

Signed-off-by: Maxime Ripard 
Reviewed-by: Heiko Stuebner 
Acked-by: Hans de Goede

clk: Include of.h in clock-provider.h

2014-09-27T06:57:50+00:00

CLK_OF_DECLARE relies on OF_DECLARE_1 that is defined in of.h. Fixes build
errors when one use CLK_OF_DECLARE but doesn't include of.h

Signed-off-by: Maxime Ripard 
Acked-by: Hans de Goede

clk: introduce clk_set_phase function & callback

2014-09-27T06:57:38+00:00

A common operation for a clock signal generator is to shift the phase of
that signal. This patch introduces a new function to the clk.h API to
dynamically adjust the phase of a clock signal. Additionally this patch
introduces support for the new function in the common clock framework
via the .set_phase call back in struct clk_ops.

Signed-off-by: Mike Turquette 
Signed-off-by: Maxime Ripard 
Reviewed-by: Heiko Stuebner 
Acked-by: Hans de Goede

clk: add gpio gated clock

2014-09-26T23:51:42+00:00

The added gpio-gate-clock is a basic clock that can be enabled and
disabled trough a gpio output. The DT binding document for the clock
is also added. For EPROBE_DEFER handling the registering of the clock
has to be delayed until of_clk_get() call time.

Signed-off-by: Jyri Sarha 
Signed-off-by: Mike Turquette