linux-toradex.git/include/linux/clk, branch v4.14-rc7

Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

2017-09-13T18:04:14+00:00

Pull clk updates from Stephen Boyd:
 "The diff is dominated by the Allwinner A10/A20 SoCs getting converted
  to the sunxi-ng framework. Otherwise, the heavy hitters are various
  drivers for SoCs like AT91, Amlogic, Renesas, and Rockchip. There are
  some other new clk drivers in here too but overall this is just a
  bunch of clk drivers for various different pieces of hardware and a
  collection of non-critical fixes for clk drivers.

  New Drivers:
   - Allwinner R40 SoCs
   - Renesas R-Car Gen3 USB 2.0 clock selector PHY
   - Atmel AT91 audio PLL
   - Uniphier PXs3 SoCs
   - ARC HSDK Board PLLs
   - AXS10X Board PLLs
   - STMicroelectronics STM32H743 SoCs

  Removed Drivers:
   - Non-compiling mb86s7x support

  Updates:
   - Allwinner A10/A20 SoCs converted to sunxi-ng framework
   - Allwinner H3 CPU clk fixes
   - Renesas R-Car D3 SoC
   - Renesas V2H and M3-W modules
   - Samsung Exynos5420/5422/5800 audio fixes
   - Rockchip fractional clk approximation fixes
   - Rockchip rk3126 SoC support within the rk3128 driver
   - Amlogic gxbb CEC32 and sd_emmc clks
   - Amlogic meson8b reset controller support
   - IDT VersaClock 5P49V5925/5P49V6901 support
   - Qualcomm MSM8996 SMMU clks
   - Various 'const' applications for struct clk_ops
   - si5351 PLL reset bugfix
   - Uniphier audio on LD11/LD20 and ethernet support on LD11/LD20/Pro4/PXs2
   - Assorted Tegra clk driver fixes"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (120 commits)
  clk: si5351: fix PLL reset
  ASoC: atmel-classd: remove aclk clock
  ASoC: atmel-classd: remove aclk clock from DT binding
  clk: at91: clk-generated: make gclk determine audio_pll rate
  clk: at91: clk-generated: create function to find best_diff
  clk: at91: add audio pll clock drivers
  dt-bindings: clk: at91: add audio plls to the compatible list
  clk: at91: clk-generated: remove useless divisor loop
  clk: mb86s7x: Drop non-building driver
  clk: ti: check for null return in strrchr to avoid null dereferencing
  clk: Don't write error code into divider register
  clk: uniphier: add video input subsystem clock
  clk: uniphier: add audio system clock
  clk: stm32h7: Add stm32h743 clock driver
  clk: gate: expose clk_gate_ops::is_enabled
  clk: nxp: clk-lpc32xx: rename clk_gate_is_enabled()
  clk: uniphier: add PXs3 clock data
  clk: hi6220: change watchdog clock source
  clk: Kconfig: Name RK805 in Kconfig for COMMON_CLK_RK808
  clk: cs2000: Add cs2000_set_saved_rate
  ...

clk: at91: add audio pll clock drivers

2017-09-01T22:46:52+00:00

This new clock driver set allows to have a fractional divided clock that
would generate a precise clock particularly suitable for audio
applications.

The main audio pll clock has two children clocks: one that is connected
to the PMC, the other that can directly drive a pad. As these two routes
have different enable bits and different dividers and divider formulas,
they are handled by two different drivers. Each of them could modify the
rate of the main audio pll parent.

The main audio pll clock can output 620MHz to 700MHz.

Signed-off-by: Nicolas Ferre 
Signed-off-by: Quentin Schulz 
Acked-by: Boris Brezillon 
Signed-off-by: Stephen Boyd

clk: sunxi-ng: Add interface to query or configure MMC timing modes.

2017-08-30T12:01:47+00:00

Starting with the A83T SoC, Allwinner introduced a new timing mode for
its MMC clocks. The new mode changes how the MMC controller sample and
output clocks are delayed to match chip and board specifics. There are
two controls for this, one on the CCU side controlling how the clocks
behave, and one in the MMC controller controlling what inputs to take
and how to route them.

In the old mode, the MMC clock had 2 child clocks providing the output
and sample clocks, which could be delayed by a number of clock cycles
measured from the MMC clock's parent.

With the new mode, the 2 delay clocks are no longer active. Instead,
the delays and associated controls are moved into the MMC controller.
The output of the MMC clock is also halved.

The difference in how things are wired between the modes means that the
clock controls and the MMC controls must match. To achieve this in a
clear, explicit way, we introduce two functions for the MMC driver to
use: one queries the hardware for the current mode set, and the other
allows the MMC driver to request a mode.

Signed-off-by: Chen-Yu Tsai 
Acked-by: Maxime Ripard 
Signed-off-by: Ulf Hansson

Merge tag 'tegra-for-4.12-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-next

2017-04-12T16:51:01+00:00

Pull Tegra clk driver updates from Thierry Reding:

This contains a bunch of fixes and cleanups, mostly to the Tegra210
clock driver.

* tag 'tegra-for-4.12-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: (24 commits)
  clk: tegra: Don't reset PLL-CX if it is already enabled
  clk: tegra: Add missing Tegra210 clocks
  clk: tegra: Propagate clk_out_x rate to parent
  clk: tegra: Fix build warnings on Tegra20/Tegra30
  clk: tegra: Mark TEGRA210_CLK_DBGAPB as always on
  clk: tegra: Add SATA seq input control
  clk: tegra: Add Tegra210 special resets
  clk: tegra: Rework pll_u
  clk: tegra: Implement reset control reset
  clk: tegra: Fix disable unused for clocks sharing enable bit
  clk: tegra: Handle UTMIPLL IDDQ
  clk: tegra: Add aclk
  clk: tegra: Add super clock mux/divider
  clk: tegra: Define Tegra210 DMIC clocks
  clk: tegra: Fix constness for peripheral clocks
  clk: tegra: Define Tegra210 DMIC sync clocks
  clk: tegra: Add CEC clock
  clk: tegra: Fix type for m field
  clk: tegra: Correct tegra210_pll_fixed_mdiv_cfg rate calculation
  clk: tegra: Don't warn for PLL defaults unnecessarily
  ...

clk: tegra: Add SATA seq input control

2017-03-20T13:26:03+00:00

This will be used by the powergating driver to ensure proper sequencer
state when the SATA domain is powergated.

Signed-off-by: Peter De Schrijver 
Signed-off-by: Thierry Reding

clk: tegra: Handle UTMIPLL IDDQ

2017-03-20T13:09:05+00:00

Export UTMIPLL IDDQ functions. These will be needed when powergating the
XUSB partition.

Signed-off-by: BH Hsieh 
Signed-off-by: Peter De Schrijver 
Signed-off-by: Thierry Reding

clk: ti: convert to use proper register definition for all accesses

2017-03-08T11:06:15+00:00

Currently, TI clock driver uses an encapsulated struct that is cast into
a void pointer to store all register addresses. This can be considered
as rather nasty hackery, and prevents from expanding the register
address field also. Instead, replace all the code to use proper struct
in place for this, which contains all the previously used data.

This patch is rather large as it is touching multiple files, but this
can't be split up as we need to avoid any boot breakage.

Signed-off-by: Tero Kristo 
Acked-by: Tony Lindgren

clk: ti: drop unnecessary MEMMAP_ADDRESSING flag

2017-03-08T11:03:07+00:00

This has been superceded by the usage of ti_clk_ll_ops for now.

Signed-off-by: Tero Kristo 
Acked-by: Tony Lindgren

clk: ti: move omap2_init_clk_clkdm under TI clock driver

2017-03-08T10:59:30+00:00

This is not needed outside the driver, so move it inside it and remove
the prototype from the public header also.

Signed-off-by: Tero Kristo 
Acked-by: Tony Lindgren

clk: ti: add clkdm_lookup to the exported functions

2017-03-08T10:58:41+00:00

This will be needed to move some additional clockdomain functionality
under clock driver.

Signed-off-by: Tero Kristo 
Acked-by: Tony Lindgren