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<title>linux-toradex.git/include/linux/intel-iommu.h, branch v4.9.16</title>
<subtitle>Linux kernel for Apalis and Colibri modules</subtitle>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/'/>
<entry>
<title>iommu/vt-d: Fix some macros that are incorrectly specified in intel-iommu</title>
<updated>2017-03-12T05:41:43+00:00</updated>
<author>
<name>CQ Tang</name>
<email>cq.tang@intel.com</email>
</author>
<published>2017-01-30T17:39:52+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=61cb3c6357fd77a2b1af49a9015955b9f82c68d4'/>
<id>61cb3c6357fd77a2b1af49a9015955b9f82c68d4</id>
<content type='text'>
commit aaa59306b0b7e0ca4ba92cc04c5db101cbb1c096 upstream.

Some of the macros are incorrect with wrong bit-shifts resulting in picking
the incorrect invalidation granularity. Incorrect Source-ID in extended
devtlb invalidation caused device side errors.

To: Joerg Roedel &lt;joro@8bytes.org&gt;
To: David Woodhouse &lt;dwmw2@infradead.org&gt;
Cc: iommu@lists.linux-foundation.org
Cc: linux-kernel@vger.kernel.org
Cc: CQ Tang &lt;cq.tang@intel.com&gt;
Cc: Ashok Raj &lt;ashok.raj@intel.com&gt;

Fixes: 2f26e0a9 ("iommu/vt-d: Add basic SVM PASID support")
Signed-off-by: CQ Tang &lt;cq.tang@intel.com&gt;
Signed-off-by: Ashok Raj &lt;ashok.raj@intel.com&gt;
Tested-by: CQ Tang &lt;cq.tang@intel.com&gt;
Signed-off-by: Joerg Roedel &lt;jroedel@suse.de&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
commit aaa59306b0b7e0ca4ba92cc04c5db101cbb1c096 upstream.

Some of the macros are incorrect with wrong bit-shifts resulting in picking
the incorrect invalidation granularity. Incorrect Source-ID in extended
devtlb invalidation caused device side errors.

To: Joerg Roedel &lt;joro@8bytes.org&gt;
To: David Woodhouse &lt;dwmw2@infradead.org&gt;
Cc: iommu@lists.linux-foundation.org
Cc: linux-kernel@vger.kernel.org
Cc: CQ Tang &lt;cq.tang@intel.com&gt;
Cc: Ashok Raj &lt;ashok.raj@intel.com&gt;

Fixes: 2f26e0a9 ("iommu/vt-d: Add basic SVM PASID support")
Signed-off-by: CQ Tang &lt;cq.tang@intel.com&gt;
Signed-off-by: Ashok Raj &lt;ashok.raj@intel.com&gt;
Tested-by: CQ Tang &lt;cq.tang@intel.com&gt;
Signed-off-by: Joerg Roedel &lt;jroedel@suse.de&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</pre>
</div>
</content>
</entry>
<entry>
<title>iommu/vt-d: Fix PASID table allocation</title>
<updated>2016-11-19T17:42:35+00:00</updated>
<author>
<name>David Woodhouse</name>
<email>dwmw2@infradead.org</email>
</author>
<published>2016-09-12T02:49:11+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=910170442944e1f8674fd5ddbeeb8ccd1877ea98'/>
<id>910170442944e1f8674fd5ddbeeb8ccd1877ea98</id>
<content type='text'>
Somehow I ended up with an off-by-three error in calculating the size of
the PASID and PASID State tables, which triggers allocations failures as
those tables unfortunately have to be physically contiguous.

In fact, even the *correct* maximum size of 8MiB is problematic and is
wont to lead to allocation failures. Since I have extracted a promise
that this *will* be fixed in hardware, I'm happy to limit it on the
current hardware to a maximum of 0x20000 PASIDs, which gives us 1MiB
tables — still not ideal, but better than before.

Reported by Mika Kuoppala &lt;mika.kuoppala@linux.intel.com&gt; and also by
Xunlei Pang &lt;xlpang@redhat.com&gt; who submitted a simpler patch to fix
only the allocation (and not the free) to the "correct" limit... which
was still problematic.

Signed-off-by: David Woodhouse &lt;dwmw2@infradead.org&gt;
Cc: stable@vger.kernel.org
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<pre>
Somehow I ended up with an off-by-three error in calculating the size of
the PASID and PASID State tables, which triggers allocations failures as
those tables unfortunately have to be physically contiguous.

In fact, even the *correct* maximum size of 8MiB is problematic and is
wont to lead to allocation failures. Since I have extracted a promise
that this *will* be fixed in hardware, I'm happy to limit it on the
current hardware to a maximum of 0x20000 PASIDs, which gives us 1MiB
tables — still not ideal, but better than before.

Reported by Mika Kuoppala &lt;mika.kuoppala@linux.intel.com&gt; and also by
Xunlei Pang &lt;xlpang@redhat.com&gt; who submitted a simpler patch to fix
only the allocation (and not the free) to the "correct" limit... which
was still problematic.

Signed-off-by: David Woodhouse &lt;dwmw2@infradead.org&gt;
Cc: stable@vger.kernel.org
</pre>
</div>
</content>
</entry>
<entry>
<title>iommu/vt-d: Clear PPR bit to ensure we get more page request interrupts</title>
<updated>2016-02-15T12:42:38+00:00</updated>
<author>
<name>David Woodhouse</name>
<email>David.Woodhouse@intel.com</email>
</author>
<published>2016-02-15T12:42:38+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=46924008273ed03bd11dbb32136e3da4cfe056e1'/>
<id>46924008273ed03bd11dbb32136e3da4cfe056e1</id>
<content type='text'>
According to the VT-d specification we need to clear the PPR bit in
the Page Request Status register when handling page requests, or the
hardware won't generate any more interrupts.

This wasn't actually necessary on SKL/KBL (which may well be the
subject of a hardware erratum, although it's harmless enough). But
other implementations do appear to get it right, and we only ever get
one interrupt unless we clear the PPR bit.

Reported-by: CQ Tang &lt;cq.tang@intel.com&gt;
Signed-off-by: David Woodhouse &lt;David.Woodhouse@intel.com&gt;
Cc: stable@vger.kernel.org
</content>
<content type='xhtml'>
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<pre>
According to the VT-d specification we need to clear the PPR bit in
the Page Request Status register when handling page requests, or the
hardware won't generate any more interrupts.

This wasn't actually necessary on SKL/KBL (which may well be the
subject of a hardware erratum, although it's harmless enough). But
other implementations do appear to get it right, and we only ever get
one interrupt unless we clear the PPR bit.

Reported-by: CQ Tang &lt;cq.tang@intel.com&gt;
Signed-off-by: David Woodhouse &lt;David.Woodhouse@intel.com&gt;
Cc: stable@vger.kernel.org
</pre>
</div>
</content>
</entry>
<entry>
<title>iommu/vt-d: Implement SVM_FLAG_PRIVATE_PASID to allocate unique PASIDs</title>
<updated>2015-10-15T14:35:32+00:00</updated>
<author>
<name>David Woodhouse</name>
<email>David.Woodhouse@intel.com</email>
</author>
<published>2015-10-15T12:59:14+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=569e4f7782fb92d0e1b395b5fb01de642dd74dcf'/>
<id>569e4f7782fb92d0e1b395b5fb01de642dd74dcf</id>
<content type='text'>
Signed-off-by: David Woodhouse &lt;David.Woodhouse@intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Signed-off-by: David Woodhouse &lt;David.Woodhouse@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>iommu/vt-d: Add callback to device driver on page faults</title>
<updated>2015-10-15T14:35:28+00:00</updated>
<author>
<name>David Woodhouse</name>
<email>David.Woodhouse@intel.com</email>
</author>
<published>2015-10-13T16:18:10+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=0204a49609824163092c32a8aeb073f7e9acc76d'/>
<id>0204a49609824163092c32a8aeb073f7e9acc76d</id>
<content type='text'>
Signed-off-by: David Woodhouse &lt;David.Woodhouse@intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Signed-off-by: David Woodhouse &lt;David.Woodhouse@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>iommu/vt-d: Implement page request handling</title>
<updated>2015-10-15T14:35:19+00:00</updated>
<author>
<name>David Woodhouse</name>
<email>David.Woodhouse@intel.com</email>
</author>
<published>2015-10-07T22:35:18+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=a222a7f0bb6c94c31cc9c755110593656f19de89'/>
<id>a222a7f0bb6c94c31cc9c755110593656f19de89</id>
<content type='text'>
Largely based on the driver-mode implementation by Jesse Barnes.

Signed-off-by: David Woodhouse &lt;David.Woodhouse@intel.com&gt;
</content>
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<pre>
Largely based on the driver-mode implementation by Jesse Barnes.

Signed-off-by: David Woodhouse &lt;David.Woodhouse@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>iommu/vt-d: Generalise DMAR MSI setup to allow for page request events</title>
<updated>2015-10-15T12:22:41+00:00</updated>
<author>
<name>David Woodhouse</name>
<email>David.Woodhouse@intel.com</email>
</author>
<published>2015-10-07T14:37:03+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=1208225cf48fa3b170b6dfe7369f15c295260755'/>
<id>1208225cf48fa3b170b6dfe7369f15c295260755</id>
<content type='text'>
Signed-off-by: David Woodhouse &lt;David.Woodhouse@intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Signed-off-by: David Woodhouse &lt;David.Woodhouse@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>iommu/vt-d: Add basic SVM PASID support</title>
<updated>2015-10-15T11:55:45+00:00</updated>
<author>
<name>David Woodhouse</name>
<email>David.Woodhouse@intel.com</email>
</author>
<published>2015-09-09T10:40:47+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=2f26e0a9c9860db290d63e9d85c2c8c09813677f'/>
<id>2f26e0a9c9860db290d63e9d85c2c8c09813677f</id>
<content type='text'>
This provides basic PASID support for endpoint devices, tested with a
version of the i915 driver.

Signed-off-by: David Woodhouse &lt;David.Woodhouse@intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This provides basic PASID support for endpoint devices, tested with a
version of the i915 driver.

Signed-off-by: David Woodhouse &lt;David.Woodhouse@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>iommu/vt-d: Add initial support for PASID tables</title>
<updated>2015-10-15T10:24:51+00:00</updated>
<author>
<name>David Woodhouse</name>
<email>David.Woodhouse@intel.com</email>
</author>
<published>2015-03-24T14:54:56+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=8a94ade4ce6df22006b96c5c9a8d6d12fce67585'/>
<id>8a94ade4ce6df22006b96c5c9a8d6d12fce67585</id>
<content type='text'>
Add CONFIG_INTEL_IOMMU_SVM, and allocate PASID tables on supported hardware.

Signed-off-by: David Woodhouse &lt;David.Woodhouse@intel.com&gt;
</content>
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<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add CONFIG_INTEL_IOMMU_SVM, and allocate PASID tables on supported hardware.

Signed-off-by: David Woodhouse &lt;David.Woodhouse@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>iommu/vt-d: Introduce intel_iommu=pasid28, and pasid_enabled() macro</title>
<updated>2015-10-15T10:24:45+00:00</updated>
<author>
<name>David Woodhouse</name>
<email>David.Woodhouse@intel.com</email>
</author>
<published>2015-09-09T10:58:59+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=ae853ddb9ad5e7c01cad3fbf016040acd961f407'/>
<id>ae853ddb9ad5e7c01cad3fbf016040acd961f407</id>
<content type='text'>
As long as we use an identity mapping to work around the worst of the
hardware bugs which caused us to defeature it and change the definition
of the capability bit, we *can* use PASID support on the devices which
advertised it in bit 28 of the Extended Capability Register.

Allow people to do so with 'intel_iommu=pasid28' on the command line.

Signed-off-by: David Woodhouse &lt;David.Woodhouse@intel.com&gt;
</content>
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<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
As long as we use an identity mapping to work around the worst of the
hardware bugs which caused us to defeature it and change the definition
of the capability bit, we *can* use PASID support on the devices which
advertised it in bit 28 of the Extended Capability Register.

Allow people to do so with 'intel_iommu=pasid28' on the command line.

Signed-off-by: David Woodhouse &lt;David.Woodhouse@intel.com&gt;
</pre>
</div>
</content>
</entry>
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