linux-toradex.git/include/linux/irq.h, branch v3.12-rc7

Remove GENERIC_HARDIRQ config option

2013-09-13T13:09:52+00:00

After the last architecture switched to generic hard irqs the config
options HAVE_GENERIC_HARDIRQS & GENERIC_HARDIRQS and the related code
for !CONFIG_GENERIC_HARDIRQS can be removed.

Signed-off-by: Martin Schwidefsky

genirq: Add irq_get_trigger_type() to get IRQ flags

2013-06-25T09:48:24+00:00

Drivers that want to get the trigger edge/level type flags for a given
interrupt have to call irq_get_irq_data(irq) to get the struct
irq_data and then irqd_get_trigger_type(irq_data) to obtain the IRQ
flags.

This is not only error prone but also unnecessary exposes the struct
irq_data to callers.

It's better to have an irq_get_trigger_type() function to obtain the
edge/level flags for an IRQ.

Signed-off-by: Javier Martinez Canillas 
Acked-by: Grant Likely 
Cc: Linus Walleij 
Cc: Samuel Ortiz 
Cc: Jason Cooper 
Cc: Andrew Lunn 
Cc: Russell King 
Cc: Ralf Baechle 
Cc: Benjamin Herrenschmidt 
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-mips@linux-mips.org
Link: http://lkml.kernel.org/r/1371228049-27080-2-git-send-email-javier.martinez@collabora.co.uk
Signed-off-by: Thomas Gleixner

genirq: irqchip: Add mask to block out invalid irqs

2013-05-29T08:57:11+00:00

Some controllers have irqs that aren't wired up and must never be used.
For the generic chip attached to an irq_domain this provides a mask that
can be used to block out particular irqs so that they never get mapped.

Signed-off-by: Grant Likely 
Link: http://lkml.kernel.org/r/1369793454-19197-2-git-send-email-grant.likely@linaro.org
Signed-off-by: Thomas Gleixner

genirq: Generic chip: Add linear irq domain support

2013-05-29T08:57:11+00:00

Provide infrastructure for irq chip implementations which work on
linear irq domains.

- Interface to allocate multiple generic chips which are associated to
  the irq domain.

- Interface to get the generic chip pointer for a particular hardware
  interrupt in the domain.

- irq domain mapping function to install the chip for a particular
  interrupt.

Note: This lacks a removal function for now.

[ Sebastian Hesselbarth: Mask cache and pointer math fixups ]

Signed-off-by: Thomas Gleixner 
Cc: Thomas Petazzoni 
Cc: Andrew Lunn 
Cc: Russell King - ARM Linux 
Cc: Jason Cooper 
Cc: Arnd Bergmann 
Cc: Jean-Francois Moine 
Cc: devicetree-discuss@lists.ozlabs.org
Cc: Rob Herring 
Cc: Jason Gunthorpe 
Cc: Gregory Clement 
Cc: Gerlando Falauto 
Cc: Rob Landley 
Acked-by: Grant Likely 
Cc: Maxime Ripard 
Cc: Ezequiel Garcia 
Cc: linux-arm-kernel@lists.infradead.org
Cc: Sebastian Hesselbarth 
Link: http://lkml.kernel.org/r/20130506142539.450634298@linutronix.de
Signed-off-by: Thomas Gleixner

genirq: irqchip: Add a mask calculation function

2013-05-29T08:57:10+00:00

Some chips have weird bit mask access patterns instead of the linear
you expect. Allow them to calculate the cached mask themself.

Signed-off-by: Thomas Gleixner 
Cc: Thomas Petazzoni 
Cc: Andrew Lunn 
Cc: Russell King - ARM Linux 
Cc: Jason Cooper 
Cc: Arnd Bergmann 
Cc: Jean-Francois Moine 
Cc: devicetree-discuss@lists.ozlabs.org
Cc: Rob Herring 
Cc: Jason Gunthorpe 
Cc: Gregory Clement 
Cc: Gerlando Falauto 
Cc: Rob Landley 
Acked-by: Grant Likely 
Cc: Maxime Ripard 
Cc: Ezequiel Garcia 
Cc: linux-arm-kernel@lists.infradead.org
Cc: Sebastian Hesselbarth 
Link: http://lkml.kernel.org/r/20130506142539.302898834@linutronix.de
Signed-off-by: Thomas Gleixner

genirq: Generic chip: Cache per irq bit mask

2013-05-29T08:57:10+00:00

Cache the per irq bit mask instead of recalculating it over and over.

Signed-off-by: Thomas Gleixner 
Cc: Thomas Petazzoni 
Cc: Andrew Lunn 
Cc: Russell King - ARM Linux 
Cc: Jason Cooper 
Cc: Arnd Bergmann 
Cc: Jean-Francois Moine 
Cc: devicetree-discuss@lists.ozlabs.org
Cc: Rob Herring 
Cc: Jason Gunthorpe 
Cc: Gregory Clement 
Cc: Gerlando Falauto 
Cc: Rob Landley 
Acked-by: Grant Likely 
Cc: Maxime Ripard 
Cc: Ezequiel Garcia 
Cc: linux-arm-kernel@lists.infradead.org
Cc: Sebastian Hesselbarth 
Link: http://lkml.kernel.org/r/20130506142539.227119865@linutronix.de
Signed-off-by: Thomas Gleixner

genirq: Generic chip: Handle separate mask registers

2013-05-29T08:57:10+00:00

There are cases where all irq_chip_type instances have separate mask
registers, making a shared mask register cache unsuitable for the
purpose.

Introduce a new flag IRQ_GC_MASK_CACHE_PER_TYPE. If set, point the per
chip mask pointer to the per chip private mask cache instead.

[ tglx: Simplified code, renamed flag and massaged changelog ]

Signed-off-by: Gerlando Falauto 
Cc: Andrew Lunn 
Cc: Joey Oravec 
Cc: Lennert Buytenhek 
Cc: Russell King - ARM Linux 
Cc: Jason Gunthorpe 
Cc: Holger Brunck 
Cc: Ezequiel Garcia 
Acked-by: Grant Likely 
Cc: Sebastian Hesselbarth 
Cc: Jason Cooper 
Cc: Arnd Bergmann 
Cc: devicetree-discuss@lists.ozlabs.org
Cc: Rob Herring 
Cc: Ben Dooks 
Cc: Gregory Clement 
Cc: Simon Guinot 
Cc: linux-arm-kernel@lists.infradead.org
Cc: Thomas Petazzoni 
Cc: Jean-Francois Moine 
Cc: Nicolas Pitre 
Cc: Rob Landley 
Cc: Maxime Ripard 
Link: http://lkml.kernel.org/r/20130506142539.152569748@linutronix.de
Signed-off-by: Thomas Gleixner

genirq: Generic chip: Add support for per chip type mask cache

2013-05-29T08:57:10+00:00

Today the same interrupt mask cache (stored within struct irq_chip_generic)
is shared between all the irq_chip_type instances. As there are instances
where each irq_chip_type uses a distinct mask register (as it is the case
for Orion SoCs), sharing a single mask cache may be incorrect.
So add a distinct pointer for each irq_chip_type, which for now
points to the original mask register within irq_chip_generic.
So no functional changes here.

[ tglx: Minor cosmetic tweaks ]

Reported-by: Joey Oravec 
Signed-off-by: Simon Guinot 
Signed-off-by: Holger Brunck 
Signed-off-by: Gerlando Falauto 
Cc: Andrew Lunn 
Cc: Lennert Buytenhek 
Cc: Russell King - ARM Linux 
Cc: Jason Gunthorpe 
Cc: Holger Brunck 
Cc: Ezequiel Garcia 
Acked-by: Grant Likely 
Cc: Sebastian Hesselbarth 
Cc: Jason Cooper 
Cc: Arnd Bergmann 
Cc: devicetree-discuss@lists.ozlabs.org
Cc: Rob Herring 
Cc: Ben Dooks 
Cc: Gregory Clement 
Cc: Simon Guinot 
Cc: linux-arm-kernel@lists.infradead.org
Cc: Thomas Petazzoni 
Cc: Jean-Francois Moine 
Cc: Nicolas Pitre 
Cc: Rob Landley 
Cc: Maxime Ripard 
Link: http://lkml.kernel.org/r/20130506142539.082226607@linutronix.de
Signed-off-by: Thomas Gleixner

x86, msi: Use IRQ remapping specific setup_msi_irqs routine

2013-01-28T11:17:25+00:00

Use seperate routines to setup MSI IRQs for both
irq_remapping_enabled cases.

Signed-off-by: Joerg Roedel 
Acked-by: Sebastian Andrzej Siewior 
Reviewed-by: Konrad Rzeszutek Wilk

x86/MSI: Support multiple MSIs in presense of IRQ remapping

2013-01-24T16:25:12+00:00

The MSI specification has several constraints in comparison with
MSI-X, most notable of them is the inability to configure MSIs
independently. As a result, it is impossible to dispatch
interrupts from different queues to different CPUs. This is
largely devalues the support of multiple MSIs in SMP systems.

Also, a necessity to allocate a contiguous block of vector
numbers for devices capable of multiple MSIs might cause a
considerable pressure on x86 interrupt vector allocator and
could lead to fragmentation of the interrupt vectors space.

This patch overcomes both drawbacks in presense of IRQ remapping
and lets devices take advantage of multiple queues and per-IRQ
affinity assignments.

Signed-off-by: Alexander Gordeev 
Cc: Bjorn Helgaas 
Cc: Suresh Siddha 
Cc: Yinghai Lu 
Cc: Matthew Wilcox 
Cc: Jeff Garzik 
Cc: Linus Torvalds 
Cc: Andrew Morton 
Cc: Peter Zijlstra 
Cc: Thomas Gleixner 
Link: http://lkml.kernel.org/r/c8bd86ff56b5fc118257436768aaa04489ac0a4c.1353324359.git.agordeev@redhat.com
Signed-off-by: Ingo Molnar