linux-toradex.git/include/linux/irq.h, branch v3.12.25

genirq: Allow forcing cpu affinity of interrupts

2014-06-06T09:40:20+00:00

commit 01f8fa4f01d8362358eb90e412bd7ae18a3ec1ad upstream.

The current implementation of irq_set_affinity() refuses rightfully to
route an interrupt to an offline cpu.

But there is a special case, where this is actually desired. Some of
the ARM SoCs have per cpu timers which require setting the affinity
during cpu startup where the cpu is not yet in the online mask.

If we can't do that, then the local timer interrupt for the about to
become online cpu is routed to some random online cpu.

The developers of the affected machines tried to work around that
issue, but that results in a massive mess in that timer code.

We have a yet unused argument in the set_affinity callbacks of the irq
chips, which I added back then for a similar reason. It was never
required so it got not used. But I'm happy that I never removed it.

That allows us to implement a sane handling of the above scenario. So
the affected SoC drivers can add the required force handling to their
interrupt chip, switch the timer code to irq_force_affinity() and
things just work.

This does not affect any existing user of irq_set_affinity().

Tagged for stable to allow a simple fix of the affected SoC clock
event drivers.

Reported-and-tested-by: Krzysztof Kozlowski 
Signed-off-by: Thomas Gleixner 
Cc: Kyungmin Park 
Cc: Marek Szyprowski 
Cc: Bartlomiej Zolnierkiewicz 
Cc: Tomasz Figa ,
Cc: Daniel Lezcano ,
Cc: Kukjin Kim 
Cc: linux-arm-kernel@lists.infradead.org,
Link: http://lkml.kernel.org/r/20140416143315.717251504@linutronix.de
Signed-off-by: Thomas Gleixner 
Signed-off-by: Jiri Slaby

Remove GENERIC_HARDIRQ config option

2013-09-13T13:09:52+00:00

After the last architecture switched to generic hard irqs the config
options HAVE_GENERIC_HARDIRQS & GENERIC_HARDIRQS and the related code
for !CONFIG_GENERIC_HARDIRQS can be removed.

Signed-off-by: Martin Schwidefsky

genirq: Add irq_get_trigger_type() to get IRQ flags

2013-06-25T09:48:24+00:00

Drivers that want to get the trigger edge/level type flags for a given
interrupt have to call irq_get_irq_data(irq) to get the struct
irq_data and then irqd_get_trigger_type(irq_data) to obtain the IRQ
flags.

This is not only error prone but also unnecessary exposes the struct
irq_data to callers.

It's better to have an irq_get_trigger_type() function to obtain the
edge/level flags for an IRQ.

Signed-off-by: Javier Martinez Canillas 
Acked-by: Grant Likely 
Cc: Linus Walleij 
Cc: Samuel Ortiz 
Cc: Jason Cooper 
Cc: Andrew Lunn 
Cc: Russell King 
Cc: Ralf Baechle 
Cc: Benjamin Herrenschmidt 
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-mips@linux-mips.org
Link: http://lkml.kernel.org/r/1371228049-27080-2-git-send-email-javier.martinez@collabora.co.uk
Signed-off-by: Thomas Gleixner

genirq: irqchip: Add mask to block out invalid irqs

2013-05-29T08:57:11+00:00

Some controllers have irqs that aren't wired up and must never be used.
For the generic chip attached to an irq_domain this provides a mask that
can be used to block out particular irqs so that they never get mapped.

Signed-off-by: Grant Likely 
Link: http://lkml.kernel.org/r/1369793454-19197-2-git-send-email-grant.likely@linaro.org
Signed-off-by: Thomas Gleixner

genirq: Generic chip: Add linear irq domain support

2013-05-29T08:57:11+00:00

Provide infrastructure for irq chip implementations which work on
linear irq domains.

- Interface to allocate multiple generic chips which are associated to
  the irq domain.

- Interface to get the generic chip pointer for a particular hardware
  interrupt in the domain.

- irq domain mapping function to install the chip for a particular
  interrupt.

Note: This lacks a removal function for now.

[ Sebastian Hesselbarth: Mask cache and pointer math fixups ]

Signed-off-by: Thomas Gleixner 
Cc: Thomas Petazzoni 
Cc: Andrew Lunn 
Cc: Russell King - ARM Linux 
Cc: Jason Cooper 
Cc: Arnd Bergmann 
Cc: Jean-Francois Moine 
Cc: devicetree-discuss@lists.ozlabs.org
Cc: Rob Herring 
Cc: Jason Gunthorpe 
Cc: Gregory Clement 
Cc: Gerlando Falauto 
Cc: Rob Landley 
Acked-by: Grant Likely 
Cc: Maxime Ripard 
Cc: Ezequiel Garcia 
Cc: linux-arm-kernel@lists.infradead.org
Cc: Sebastian Hesselbarth 
Link: http://lkml.kernel.org/r/20130506142539.450634298@linutronix.de
Signed-off-by: Thomas Gleixner

genirq: irqchip: Add a mask calculation function

2013-05-29T08:57:10+00:00

Some chips have weird bit mask access patterns instead of the linear
you expect. Allow them to calculate the cached mask themself.

Signed-off-by: Thomas Gleixner 
Cc: Thomas Petazzoni 
Cc: Andrew Lunn 
Cc: Russell King - ARM Linux 
Cc: Jason Cooper 
Cc: Arnd Bergmann 
Cc: Jean-Francois Moine 
Cc: devicetree-discuss@lists.ozlabs.org
Cc: Rob Herring 
Cc: Jason Gunthorpe 
Cc: Gregory Clement 
Cc: Gerlando Falauto 
Cc: Rob Landley 
Acked-by: Grant Likely 
Cc: Maxime Ripard 
Cc: Ezequiel Garcia 
Cc: linux-arm-kernel@lists.infradead.org
Cc: Sebastian Hesselbarth 
Link: http://lkml.kernel.org/r/20130506142539.302898834@linutronix.de
Signed-off-by: Thomas Gleixner

genirq: Generic chip: Cache per irq bit mask

2013-05-29T08:57:10+00:00

Cache the per irq bit mask instead of recalculating it over and over.

Signed-off-by: Thomas Gleixner 
Cc: Thomas Petazzoni 
Cc: Andrew Lunn 
Cc: Russell King - ARM Linux 
Cc: Jason Cooper 
Cc: Arnd Bergmann 
Cc: Jean-Francois Moine 
Cc: devicetree-discuss@lists.ozlabs.org
Cc: Rob Herring 
Cc: Jason Gunthorpe 
Cc: Gregory Clement 
Cc: Gerlando Falauto 
Cc: Rob Landley 
Acked-by: Grant Likely 
Cc: Maxime Ripard 
Cc: Ezequiel Garcia 
Cc: linux-arm-kernel@lists.infradead.org
Cc: Sebastian Hesselbarth 
Link: http://lkml.kernel.org/r/20130506142539.227119865@linutronix.de
Signed-off-by: Thomas Gleixner

genirq: Generic chip: Handle separate mask registers

2013-05-29T08:57:10+00:00

There are cases where all irq_chip_type instances have separate mask
registers, making a shared mask register cache unsuitable for the
purpose.

Introduce a new flag IRQ_GC_MASK_CACHE_PER_TYPE. If set, point the per
chip mask pointer to the per chip private mask cache instead.

[ tglx: Simplified code, renamed flag and massaged changelog ]

Signed-off-by: Gerlando Falauto 
Cc: Andrew Lunn 
Cc: Joey Oravec 
Cc: Lennert Buytenhek 
Cc: Russell King - ARM Linux 
Cc: Jason Gunthorpe 
Cc: Holger Brunck 
Cc: Ezequiel Garcia 
Acked-by: Grant Likely 
Cc: Sebastian Hesselbarth 
Cc: Jason Cooper 
Cc: Arnd Bergmann 
Cc: devicetree-discuss@lists.ozlabs.org
Cc: Rob Herring 
Cc: Ben Dooks 
Cc: Gregory Clement 
Cc: Simon Guinot 
Cc: linux-arm-kernel@lists.infradead.org
Cc: Thomas Petazzoni 
Cc: Jean-Francois Moine 
Cc: Nicolas Pitre 
Cc: Rob Landley 
Cc: Maxime Ripard 
Link: http://lkml.kernel.org/r/20130506142539.152569748@linutronix.de
Signed-off-by: Thomas Gleixner

genirq: Generic chip: Add support for per chip type mask cache

2013-05-29T08:57:10+00:00

Today the same interrupt mask cache (stored within struct irq_chip_generic)
is shared between all the irq_chip_type instances. As there are instances
where each irq_chip_type uses a distinct mask register (as it is the case
for Orion SoCs), sharing a single mask cache may be incorrect.
So add a distinct pointer for each irq_chip_type, which for now
points to the original mask register within irq_chip_generic.
So no functional changes here.

[ tglx: Minor cosmetic tweaks ]

Reported-by: Joey Oravec 
Signed-off-by: Simon Guinot 
Signed-off-by: Holger Brunck 
Signed-off-by: Gerlando Falauto 
Cc: Andrew Lunn 
Cc: Lennert Buytenhek 
Cc: Russell King - ARM Linux 
Cc: Jason Gunthorpe 
Cc: Holger Brunck 
Cc: Ezequiel Garcia 
Acked-by: Grant Likely 
Cc: Sebastian Hesselbarth 
Cc: Jason Cooper 
Cc: Arnd Bergmann 
Cc: devicetree-discuss@lists.ozlabs.org
Cc: Rob Herring 
Cc: Ben Dooks 
Cc: Gregory Clement 
Cc: Simon Guinot 
Cc: linux-arm-kernel@lists.infradead.org
Cc: Thomas Petazzoni 
Cc: Jean-Francois Moine 
Cc: Nicolas Pitre 
Cc: Rob Landley 
Cc: Maxime Ripard 
Link: http://lkml.kernel.org/r/20130506142539.082226607@linutronix.de
Signed-off-by: Thomas Gleixner

x86, msi: Use IRQ remapping specific setup_msi_irqs routine

2013-01-28T11:17:25+00:00

Use seperate routines to setup MSI IRQs for both
irq_remapping_enabled cases.

Signed-off-by: Joerg Roedel 
Acked-by: Sebastian Andrzej Siewior 
Reviewed-by: Konrad Rzeszutek Wilk