linux-toradex.git/include/linux/irqchip, branch v3.17-rc4

Merge branch 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

2014-08-06T00:38:45+00:00

Pull irq updates from Thomas Gleixner:
 "Nothing spectacular from the irq department this time:
   - overhaul of the crossbar chip driver
   - overhaul of the spear shirq chip driver
   - support for the atmel-aic chip
   - code move from arch to drivers
   - the usual tiny fixlets
   - two reverts worth to mention which undo the too simple attempt of
     supporting wakeup interrupts on shared interrupt lines"

* 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (41 commits)
  Revert "irq: Warn when shared interrupts do not match on NO_SUSPEND"
  Revert "PM / sleep / irq: Do not suspend wakeup interrupts"
  irq: Warn when shared interrupts do not match on NO_SUSPEND
  irqchip: atmel-aic: Define irq fixups for atmel SoCs
  irqchip: atmel-aic: Implement RTC irq fixup
  irqchip: atmel-aic: Add irq fixup infrastructure
  irqchip: atmel-aic: Add atmel AIC/AIC5 drivers
  irqchip: atmel-aic: Move binding doc to interrupt-controller directory
  genirq: generic chip: Export irq_map_generic_chip function
  PM / sleep / irq: Do not suspend wakeup interrupts
  irqchip: or1k-pic: Migrate from arch/openrisc/
  irqchip: crossbar: Allow for quirky hardware with direct hardwiring of GIC
  documentation: dt: omap: crossbar: Add description for interrupt consumer
  irqchip: crossbar: Introduce centralized check for crossbar write
  irqchip: crossbar: Introduce ti, max-crossbar-sources to identify valid crossbar mapping
  irqchip: crossbar: Add kerneldoc for crossbar_domain_unmap callback
  irqchip: crossbar: Set cb pointer to null in case of error
  irqchip: crossbar: Change the goto naming
  irqchip: crossbar: Return proper error value
  irqchip: crossbar: Fix kerneldoc warning
  ...

arm64: gicv3: Allow GICv3 compilation with older binutils

2014-07-25T12:12:15+00:00

GICv3 introduces new system registers accessible with the full msr/mrs
syntax (e.g. mrs x0, Sop0_op1_CRm_CRn_op2). However, only recent
binutils understand the new syntax. This patch introduces msr_s/mrs_s
assembly macros which generate the equivalent instructions above and
converts the existing GICv3 code (both drivers/irqchip/ and
arch/arm64/kernel/).

Signed-off-by: Catalin Marinas 
Reported-by: Olof Johansson 
Tested-by: Olof Johansson 
Suggested-by: Mark Rutland 
Acked-by: Mark Rutland 
Acked-by: Jason Cooper 
Cc: Will Deacon 
Cc: Marc Zyngier

Merge tag 'tags/deps-irqchip-gic-3.17' into irqchip/core

2014-07-18T20:56:39+00:00

From local branch irqchip/gic, this is topic branch that was set up to
facilitate merging other changes depending on the new GICv3 driver.

irqchip: gic-v3: Initial support for GICv3

2014-07-08T22:11:47+00:00

The Generic Interrupt Controller (version 3) offers services that are
similar to GICv2, with a number of additional features:
- Affinity routing based on the CPU MPIDR (ARE)
- System register for the CPU interfaces (SRE)
- Support for more that 8 CPUs
- Locality-specific Peripheral Interrupts (LPIs)
- Interrupt Translation Services (ITS)

This patch adds preliminary support for GICv3 with ARE and SRE,
non-secure mode only. It relies on higher exception levels to grant ARE
and SRE access.

Support for LPI and ITS will be added at a later time.

Cc: Thomas Gleixner 
Cc: Jason Cooper 
Reviewed-by: Zi Shen Lim 
Reviewed-by: Christoffer Dall 
Reviewed-by: Tirumalesh Chalamarla 
Reviewed-by: Yun Wu 
Reviewed-by: Zhen Lei 
Tested-by: Tirumalesh Chalamarla
Tested-by: Radha Mohan Chintakuntla 
Acked-by: Radha Mohan Chintakuntla 
Acked-by: Catalin Marinas 
Signed-off-by: Marc Zyngier 
Reviewed-by: Mark Rutland 
Link: https://lkml.kernel.org/r/1404140510-5382-3-git-send-email-marc.zyngier@arm.com
Signed-off-by: Jason Cooper

irqchip: spear_shirq: Move private structs to source

2014-06-24T12:37:18+00:00

No point in having them in a separate header file. Make the init
functions static.

Signed-off-by: Thomas Gleixner 
Link: https://lkml.kernel.org/r/20140619212713.038658058@linutronix.de
Acked-by: Viresh Kumar 
Signed-off-by: Jason Cooper

irqchip: gic: Use mask field in GICC_IAR

2014-05-19T00:35:23+00:00

Bit[9:0] is interrupt ID field in GICC_IAR. Bit[12:10] is CPU ID field,
and others are reserved.

So we should use GICC_IAR_INT_ID_MASK to get interrupt ID. It's not a good way
to use ~0x1c00 (CPU ID field) to get interrupt ID.

Signed-off-by: Haojian Zhuang 
Link: https://lkml.kernel.org/r/1399795571-17231-3-git-send-email-haojian.zhuang@linaro.org
Signed-off-by: Jason Cooper

Merge tag 'omap-for-v3.15/crossbar-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/drivers

2014-03-09T07:32:26+00:00

Merge OMAP crossbar support from Tony Lindgren:

Add support for GIC crossbar that routes interrupts on newer omaps.

Looks like people wanted these merged via the omap tree as it's
the only user for the GIC crossbar.

* tag 'omap-for-v3.15/crossbar-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ARM: DRA: Enable Crossbar IP support for DRA7XX
  ARM: OMAP4+: Correct Wakeup-gen code to use physical irq number
  DRIVERS: IRQCHIP: CROSSBAR: Add support for Crossbar IP
  DRIVERS: IRQCHIP: IRQ-GIC: Add support for routable irqs

Signed-off-by: Olof Johansson

irqchip: support cascaded VICs

2014-02-13T10:21:21+00:00

This adds support for a VIC to be cascaded off another IRQ.
On the Integrator/AP logical module IM-PD1 there is a VIC
cascaded off the central FPGA IRQ controller so this is
needed for that to work out.

In order for the plug-in board to be able to register all
the devices with their IRQs relative to the offset of the
base obtained for the cascaded VIC, the base IRQ number
is passed back to the caller.

Cc: Thomas Gleixner 
Signed-off-by: Linus Walleij

DRIVERS: IRQCHIP: CROSSBAR: Add support for Crossbar IP

2014-02-05T14:38:34+00:00

Some socs have a large number of interrupts requests to service
the needs of its many peripherals and subsystems. All of the
interrupt lines from the subsystems are not needed at the same
time, so they have to be muxed to the irq-controller appropriately.
In such places a interrupt controllers are preceded by an CROSSBAR
that provides flexibility in muxing the device requests to the controller
inputs.

This driver takes care a allocating a free irq and then configuring the
crossbar IP as a part of the mpu's irqchip callbacks. crossbar_init should
be called right before the irqchip_init, so that it is setup to handle the
irqchip callbacks.

Cc: Thomas Gleixner 
Cc: Linus Walleij 
Cc: Santosh Shilimkar 
Cc: Russell King 
Cc: Tony Lindgren 
Cc: Rajendra Nayak 
Cc: Marc Zyngier 
Cc: Grant Likely 
Cc: Rob Herring 
Signed-off-by: Sricharan R 
Acked-by: Kumar Gala  (for DT binding portion)
Acked-by: Santosh Shilimkar 
Acked-by: Linus Walleij 
Acked-by: Thomas Gleixner

DRIVERS: IRQCHIP: IRQ-GIC: Add support for routable irqs

2014-02-05T14:38:00+00:00

In some socs the gic can be preceded by a crossbar IP which
routes the peripheral interrupts to the gic inputs. The peripheral
interrupts are associated with a fixed crossbar input line and the
crossbar routes that to one of the free gic input line.

The DT entries for peripherals provides the fixed crossbar input line
as its interrupt number and the mapping code should associate this with
a free gic input line. This patch adds the support inside the gic irqchip
to handle such routable irqs. The routable irqs are registered in a linear
domain. The registered routable domain's callback should be implemented
to get a free irq and to configure the IP to route it.

Cc: Thomas Gleixner 
Cc: Linus Walleij 
Cc: Santosh Shilimkar 
Cc: Russell King 
Cc: Tony Lindgren 
Cc: Rajendra Nayak 
Cc: Marc Zyngier 
Cc: Grant Likely 
Cc: Rob Herring 
Signed-off-by: Sricharan R 
Reviewed-by: Thomas Gleixner 
Acked-by: Santosh Shilimkar 
Acked-by: Linus Walleij