linux-toradex.git/include/linux/mfd/samsung, branch v4.16-rc4

Merge remote-tracking branches 'regulator/topic/pwm', 'regulator/topic/qcom-spmi', 'regulator/topic/rk808' and 'regulator/topic/s2mps11' into regulator-next

2016-05-13T13:23:46+00:00

regulator: s2mps11: Set default ramp delay for S2MPS11 LDOs

2016-04-18T16:31:38+00:00

Driver did not provide default value for ramp delay for LDOs which lead
to warning in dmesg, e.g. on Odroid XU4:

[    1.486076] vdd_ldo9: ramp_delay not set
[    1.506875] vddq_mmc2: ramp_delay not set
[    1.523766] vdd_ldo15: ramp_delay not set
[    1.544702] vdd_sd: ramp_delay not set

The datasheet for all the S2MPS1x family is inconsistent here and does
not specify unambiguously the value of ramp delay for LDO. It mentions
30 mV/us in one timing diagram but then omits it completely in LDO
regulator characteristics table (it is specified for bucks).

However the vendor kernels for Galaxy S5 and Odroid XU3 use values of 12
mV/us or 24 mV/us.

Without the ramp delay value the consumers do not wait for voltage
settle after changing it. Although the proper value of ramp delay for
LDOs is unknown, it seems safer to use at least some value from
reference kernel than to leave it unset.

Signed-off-by: Krzysztof Kozlowski 
Signed-off-by: Mark Brown

regulator: s2mps11: Fix invalid selector mask and voltages for buck9

2016-03-28T09:36:30+00:00

The buck9 regulator of S2MPS11 PMIC had incorrect vsel_mask (0xff
instead of 0x1f) thus reading entire register as buck9's voltage. This
effectively caused regulator core to interpret values as higher voltages
than they were and then to set real voltage much lower than intended.

The buck9 provides power to other regulators, including LDO13
and LDO19 which supply the MMC2 (SD card). On Odroid XU3/XU4 the lower
voltage caused SD card detection errors on Odroid XU3/XU4:
	mmc1: card never left busy state
	mmc1: error -110 whilst initialising SD card

During driver probe the regulator core was checking whether initial
voltage matches the constraints. With incorrect vsel_mask of 0xff and
default value of 0x50, the core interpreted this as 5 V which is outside
of constraints (3-3.775 V). Then the regulator core was adjusting the
voltage to match the constraints. With incorrect vsel_mask this new
voltage mapped to a vere low voltage in the driver.

Signed-off-by: Krzysztof Kozlowski 
Reviewed-by: Javier Martinez Canillas 
Tested-by: Javier Martinez Canillas 
Signed-off-by: Mark Brown 
Cc:

rtc: s5m: Make register configuration per S2MPS device to remove exceptions

2016-01-11T19:21:55+00:00

Before updating time and alarm the driver must set appropriate mask in
UDR register. For that purpose the driver uses common register
configuration and a lot of exceptions per device in the code. The
exceptions are not obvious, for example except the change in the logic
sometimes the fields are swapped (WUDR and AUDR between S2MPS14 and
S2MPS15). This leads to quite complicated code.

Try to make it more obvious by:
1. Documenting the UDR masks for devices and operations.
2. Adding fields in register configuration structure for each operation
   (read time, write time and alarm).
3. Splitting the configuration per S2MPS13, S2MPS14 and S2MPS15 thus
   removing exceptions for them.

Signed-off-by: Krzysztof Kozlowski 
Reviewed-by: Alim Akhtar 
Tested-by: Alim Akhtar 
Acked-by: Lee Jones 
Signed-off-by: Alexandre Belloni

rtc: s5m.c: Add support for S2MPS15 RTC

2015-11-23T10:34:38+00:00

RTC found in s2mps15 is almost same as one found on s2mps13
with few differences in RTC_UPDATE register fields, like:
1> Bit[4] and Bit[1] are reversed
   - On s2mps13
          WUDR -> bit[4], AUDR -> bit[1]
   - On s2mps15
	  WUDR -> bit[1], AUDR -> bit[4]
2> In case of s2mps13, for alarm register, need to set both
   WDUR and ADUR high, whereas for s2mps15 only set AUDR to high.
3> On s2mps15, WUDR, RUDR and AUDR functions should never be used
   at the same time.

This patch add required changes to enable s2mps15 rtc timer.

Signed-off-by: Alim Akhtar 
Reviewed-by: Krzysztof Kozlowski 
Acked-by: Alexandre Belloni 
Signed-off-by: Lee Jones

mfd: sec: Add support for S2MPS15 PMIC

2015-11-23T10:33:16+00:00

Add support for S2MPS15 PMIC which is similar to S2MPS11 PMIC. The S2MPS15
PMIC supports 27 LDO regulators, 10 buck regulators, RTC, three 32.768KHz
clock outputs and battery charger. This patch adds initial support for
LDO and buck regulators of S2MPS15 device.

Signed-off-by: Thomas Abraham 
Signed-off-by: Alim Akhtar 
Reviewed-by: Krzysztof Kozlowski 
[Alim: Added s2mps15_devs like rtc and clk and related changes]
Signed-off-by: Lee Jones

mfd: sec-core: Disable buck voltage reset on watchdog falling edge

2015-10-30T17:20:37+00:00

The WRSTBI bit (disabled by default but enabled by bootloader), when
set, is responsible for resetting voltages to default values of
certain bucks on falling edge of Warm Reset Input pin from AP.

However on some boards (with S2MPS13) the pin is pulled down so any
suspend will effectively trigger the reset of bucks supplying the power
to the little and big cores. In the same time when resuming, these bucks
must provide voltage greater or equal to voltage before suspend to match
the frequency chosen by cpufreq. If voltage (default value of voltage
after reset) is lower than one set by cpufreq before suspend, then
system will hang during resuming.

Signed-off-by: Krzysztof Kozlowski 
Reported-by: Bartlomiej Zolnierkiewicz 
Tested-by: Bartlomiej Zolnierkiewicz 
Signed-off-by: Lee Jones

mfd: s2mps11: Add manual shutdown method for Odroid XU3

2015-10-26T14:49:04+00:00

On Odroid XU3 board (with S2MPS11 PMIC) the PWRHOLD bit in CTRL1
register must be manually set to 0 before initiating power off sequence.

One of usual power down methods for Exynos based devices looks like:
1. PWRHOLD pin of PMIC is connected to PSHOLD of Exynos SoC.
2. Exynos holds up this pin during system operation.
3. ACOKB pin of PMIC is pulled up to VBATT and optionally to pin in
   other device.
4. When PWRHOLD/PSHOLD goes low, the PMIC will turn off the power if
   ACOKB goes high.

On Odroid XU3 family the difference is in (3) - the ACOKB is grounded.
This means that PMIC must manually set PWRHOLD field to low and then
wait for signal from Application Processor (the usual change in
PWRHOLD/PSHOLD pin will actually cut off the power).

The patch adds respective binding allowing Odroid XU3 device to be
powered off.

Signed-off-by: Krzysztof Kozlowski 
Reported-by: Anand Moon 
Tested-by: Anand Moon 
Reviewed-by: Javier Martinez Canillas 
Signed-off-by: Lee Jones

drivers/rtc/rtc-s5m.c: add support for S2MPS13 RTC

2015-04-17T13:04:01+00:00

The S2MPS13 RTC is almost the same as S2MPS14. The differences when
updating alarm are:
1. Set WUDR+AUDR field instead of WUDR+RUDR.
2. Clear the AUDR field later (it is not auto-cleared).

Signed-off-by: Krzysztof Kozlowski 
Cc: Alexandre Belloni 
Cc: Alessandro Zummo 
Signed-off-by: Andrew Morton 
Signed-off-by: Linus Torvalds

mfd: sec: Fix RTC alarm interrupt number on S2MPS11

2015-04-09T09:26:54+00:00

The RTC on S2MPS11 is the same as S2MPS14. However interrupt numbers of
RTC alarms 0 and 1 were inversed between these two devices. So when
rtc-s5m driver requested S2MPS14_IRQ_RTCA0 interrupt, it matched to
S2MPS11_IRQ_RTCA1, not RTCA0.

Fix this by using consistent RTC alarm interrupt numbers and adding a
BUILD_BUG_ON for future generations.

Signed-off-by: Krzysztof Kozlowski 
Signed-off-by: Lee Jones