linux-toradex.git/include/linux/mlx5/device.h, branch v5.10-rc3

net/mlx5: Add support for fw live patch event

2020-10-09T19:06:53+00:00

Firmware live patch event notifies the driver that the firmware was just
updated using live patch. In such case the driver should not reload or
re-initiate entities, part to updating the firmware version and
re-initiate the firmware tracer which can be updated by live patch with
new strings database to help debugging an issue.

Signed-off-by: Moshe Shemesh 
Reviewed-by: Saeed Mahameed 
Signed-off-by: Jakub Kicinski

net/mlx5e: Add CQE compression support for multi-strides packets

2020-09-15T18:59:53+00:00

Add CQE compression support for completions of packets that span
multiple strides in a Striding RQ, per the HW capability.
In our memory model, we use small strides (256B as of today) for the
non-linear SKB mode. This feature allows CQE compression to work also
for multiple strides packets. In this case decompressing the mini CQE
array will use stride index provided by HW as part of the mini CQE.
Before this feature, compression was possible only for single-strided
packets, i.e. for packets of size up to 256 bytes when in non-linear
mode, and the index was maintained by SW.
This feature is supported for ConnectX-5 and above.

Feature performance test:
This was whitebox-tested, we reduced the PCI speed from 125Gb/s to
62.5Gb/s to overload pci and manipulated mlx5 driver to drop incoming
packets before building the SKB to achieve low cpu utilization.
Outcome is low cpu utilization and bottleneck on pci only.
Test setup:
Server: Intel(R) Xeon(R) Silver 4108 CPU @ 1.80GHz server, 32 cores
NIC: ConnectX-6 DX.
Sender side generates 300 byte packets at full pci bandwidth.
Receiver side configuration:
Single channel, one cpu processing with one ring allocated. Cpu utilization
is ~20% while pci bandwidth is fully utilized.
For the generated traffic and interface MTU of 4500B (to activate the
non-linear SKB mode), packet rate improvement is about 19% from ~17.6Mpps
to ~21Mpps.
Without this feature, counters show no CQE compression blocks for
this setup, while with the feature, counters show ~20.7Mpps compressed CQEs
in ~500K compression blocks.

Signed-off-by: Ofer Levi 
Reviewed-by: Tariq Toukan 
Signed-off-by: Saeed Mahameed

RDMA/mlx5: Set mkey relaxed ordering by UMR with ConnectX-7

2020-07-27T14:19:00+00:00

Up to ConnectX-7 UMR is not used when user passes relaxed ordering access
flag. ConnectX-7 supports setting relaxed ordering read/write mkey
attribute by UMR, indicated by new HCA capabilities.

With ConnectX-7 driver uses UMR when user set relaxed ordering access
flag, in contrast to previous silicon models. Specifically it includes
setting relvant flags of mkey context mask in UMR control segment, and
relaxed ordering write and read flags in UMR mkey context segment.

Link: https://lore.kernel.org/r/20200716105248.1423452-4-leon@kernel.org
Signed-off-by: Meir Lichtinger 
Reviewed-by: Michael Guralnik 
Signed-off-by: Leon Romanovsky 
Signed-off-by: Jason Gunthorpe

RDMA/mlx5: Use MLX5_SET macro instead of local structure

2020-07-27T14:19:00+00:00

Use generic mlx5 structure defined in mlx5_ifc.h to represent ConnectX
device data structures instead of using structure defined specifically for
mlx5_ib module.

Link: https://lore.kernel.org/r/20200716105248.1423452-3-leon@kernel.org
Signed-off-by: Meir Lichtinger 
Signed-off-by: Leon Romanovsky 
Signed-off-by: Jason Gunthorpe

net/mlx5: Add interface changes required for VDPA

2020-07-16T05:21:29+00:00

Rename mlx5_ifc_device_virtio_emulation_cap_bits to
mlx5_ifc_virtio_emulation_cap_bits to match names produced by the
tools producing these auto generated files.

In addition missing capabilities that will be required by VDPA
implementation.

Signed-off-by: Eli Cohen 
Reviewed-by: Parav Pandit 
Signed-off-by: Saeed Mahameed

net/mlx5: kTLS, Improve TLS params layout structures

2020-06-27T20:50:46+00:00

Add explicit WQE segment structures for the TLS static and progress
params.
According to the HW spec, TISN is not part of the progress params context,
take it out of it.
Rename the control segment tisn field as it could hold either a TIS or
a TIR number.

Signed-off-by: Tariq Toukan 
Signed-off-by: Saeed Mahameed

net/mlx5: Introduce TLS RX offload hardware bits

2020-04-28T19:45:18+00:00

Add TLS RX offload related IFC hardware fields and enumerations.

Signed-off-by: Tariq Toukan 
Reviewed-by: Maxim Mikityanskiy 
Reviewed-by: Boris Pismenny 
Signed-off-by: Saeed Mahameed

net/mlx5: Add structure and defines for pci sync for fw update event

2020-04-28T19:45:18+00:00

Add needed structure layouts and defines for pci sync for fw update
event. The downstream patches will include event handlers for this event
type.

Signed-off-by: Moshe Shemesh 
Reviewed-by: Tariq Toukan 
Signed-off-by: Saeed Mahameed

net/mlx5: Refactor imm_inval_pkey field in cqe struct

2020-04-28T19:45:15+00:00

The imm_inval_pkey field can hold four different types of data,
depends on the usage, the data could be one of the below:
- Immediate field of the received message
- Invalidate rkey
- Pkey of the packet
- Flow table metadata

Current implementation doesn't reflect the intended usage of the
field at usage time.

Reflect the different types by replace this field with a union,
modify code where this field is used to reflect its intended
usage.

Signed-off-by: Raed Salem 
Reviewed-by: Huy Nguyen 
Reviewed-by: Tariq Toukan 
Signed-off-by: Saeed Mahameed

net/mlx5: Introduce IPsec Connect-X offload hardware bits and structures

2020-04-28T19:44:45+00:00

Add IPsec offload related IFC structs, layouts and enumerations.

Signed-off-by: Raed Salem 
Reviewed-by: Tariq Toukan 
Signed-off-by: Saeed Mahameed