linux-toradex.git/include/linux/mmc/sdhci.h, branch v3.4.16

mmc: sdhci: add quirk for keeping card power during suspend

2012-03-27T16:20:08+00:00

Add quirk SDHCI_QUIRK2_HOST_OFF_CARD_ON to cater for the case when the
card keeps power during suspend but the host controller does not i.e.
the card power is not controlled by the host controller.  In that
case, the controller must be fully reset on resume.

Signed-off-by: Adrian Hunter 
Signed-off-by: Chris Ball

mmc: host: Adds support for eMMC 4.5 HS200 mode

2012-01-12T20:17:16+00:00

This patch adds support for the HS200 mode on the host side.
Also enables the tuning feature required when the HS200 mode
is selected.

Signed-off-by: Girish K S 
Signed-off-by: Chris Ball

mmc: sdhci-pci: remove SDHCI_QUIRK2_OWN_CARD_DETECTION

2012-01-12T04:58:47+00:00

Even if a driver provides separate card detection, an interrupt
is still needed to abort mmc requests that are in progress.
SDHCI_QUIRK2_OWN_CARD_DETECTION prevents that, so remove it.

Signed-off-by: Adrian Hunter 
Signed-off-by: Chris Ball

mmc: sdhci-pci: add runtime pm support

2011-10-26T20:32:20+00:00

Ths patch allows runtime PM for sdhci-pci, runtime suspending after
inactivity of 50ms and ensuring runtime resume before SDHC registers
are accessed.  During runtime suspend, interrupts are masked.
The host controller state is restored at runtime resume.

For Medfield, the host controller's card detect mechanism is
supplanted by an always-on GPIO which provides for card detect wake-up.

Signed-off-by: Adrian Hunter 
Signed-off-by: Chris Ball

mmc: Standardize header file inclusion checks.

2011-07-20T21:20:48+00:00

Standardize the checks for multiple MMC header file inclusion,
including adding comments to terminating #endif's, and fixing
one incorrect comment.

Signed-off-by: Robert P. J. Day 
Signed-off-by: Chris Ball

mmc: sdhci: Auto-CMD23 support.

2011-05-25T20:51:40+00:00

Enables Auto-CMD23 support where available (SDHCI 3.0 controllers)

Signed-off-by: Andrei Warkentin 
Tested-by: Arindam Nath 
Signed-off-by: Chris Ball

mmc: sdhci: Implement MMC_CAP_CMD23 for SDHCI.

2011-05-25T20:49:00+00:00

Implements support for multiblock transfers bounded
by SET_BLOCK_COUNT (CMD23).

Signed-off-by: Andrei Warkentin 
Signed-off-by: Chris Ball

mmc: sdhci: add support for retuning mode 1

2011-05-25T03:53:48+00:00

Host Controller v3.00 can support retuning modes 1,2 or 3 depending on
the bits 46-47 of the Capabilities register. Also, the timer count for
retuning is indicated by bits 40-43 of the same register. We initialize
timer_list for retuning the first time we execute tuning procedure. This
condition is indicated by SDHCI_NEEDS_RETUNING not being set. Since
retuning mode 1 sets a limit of 4MB on the maximum data length, we set
max_blk_count appropriately. Once the tuning timer expires, we set
SDHCI_NEEDS_RETUNING flag, and if the flag is set, we execute tuning
procedure before sending the next command. We need to restore mmc_request
structure after executing retuning procedure since host->mrq is used
inside the procedure to send CMD19. We also disable and re-enable this
flag during suspend and resume respectively, as per the spec v3.00.

Tested by Zhangfei Gao with a Toshiba uhs card and general hs card,
on mmp2 in SDMA mode.

Signed-off-by: Arindam Nath 
Reviewed-by: Philip Rakity 
Tested-by: Philip Rakity 
Acked-by: Zhangfei Gao 
Signed-off-by: Chris Ball

mmc: sdhci: add support for programmable clock mode

2011-05-25T03:53:48+00:00

Host Controller v3.00 supports programmable clock mode as an optional
feature. The support for this mode is indicated by non-zero value in
bits 48-55 of the Capabilities register. If supported, the actual
value of Clock Multiplier is one more than the value provided in the
bit fields. We only set Clock Generator Select (bit 5) and SDCLK
Frequency Select (bits 8-15) of the Clock Control register in case
Preset Value Enable is not set, otherwise these fields are automatically
set by the Host Controller based on the UHS mode selected. Also, since
the maximum and minimum clock frequency in this mode can be
(Base Clock * Clock Mul) and (Base Clock * Clock Mul)/1024 respectively,
f_max and f_min have been recalculated to reflect this change.

Tested by Zhangfei Gao with a Toshiba uhs card and general hs card,
on mmp2 in SDMA mode.

Signed-off-by: Arindam Nath 
Reviewed-by: Philip Rakity 
Tested-by: Philip Rakity 
Acked-by: Zhangfei Gao 
Signed-off-by: Chris Ball

mmc: sd: add support for tuning during uhs initialization

2011-05-25T03:53:46+00:00

Host Controller needs tuning during initialization to operate SDR50
and SDR104 UHS-I cards. Whether SDR50 mode actually needs tuning is
indicated by bit 45 of the Host Controller Capabilities register.
A new command CMD19 has been defined in the Physical Layer spec
v3.01 to request the card to send tuning pattern.

We enable Buffer Read Ready interrupt at the very begining of tuning
procedure, because that is the only interrupt generated by the Host
Controller during tuning. We program the block size to 64 in the
Block Size register. We make sure that DMA Enable and Multi Block
Select in the Transfer Mode register are set to 0 before actually
sending CMD19. The tuning block is sent by the card to the Host
Controller using DAT lines, so we set Data Present Select (bit 5) in
the Command register. The Host Controller is responsible for doing
the verfication of tuning block sent by the card at the hardware
level. After sending CMD19, we wait for Buffer Read Ready interrupt.
In case we don't receive an interrupt after the specified timeout
value, we fall back on fixed sampling clock by setting Execute
Tuning (bit 6) and Sampling Clock Select (bit 7) of Host Control2
register to 0. Before exiting the tuning procedure, we disable Buffer
Read Ready interrupt and re-enable other interrupts.

Tested by Zhangfei Gao with a Toshiba uhs card and general hs card,
on mmp2 in SDMA mode.

Signed-off-by: Arindam Nath 
Reviewed-by: Philip Rakity 
Tested-by: Philip Rakity 
Acked-by: Zhangfei Gao 
Signed-off-by: Chris Ball