linux-toradex.git/include/linux/mtd, branch v2.6.35-rc3

mtd: nand: support alternate BB marker locations on MLC

2010-05-14T00:56:12+00:00

This is a slightly modified version of a patch submitted last year by
Reuben Dowle .  His original comments follow:

This patch adds support for some MLC NAND flashes that place the BB
marker in the LAST page of the bad block rather than the FIRST page used
for SLC NAND and other types of MLC nand.

Lifted from Samsung datasheet for K9LG8G08U0A (1Gbyte MLC NAND):
"
Identifying Initial Invalid Block(s)
All device locations are erased(FFh) except locations where the initial
invalid block(s) information is written prior to shipping. The initial
invalid block(s) status is defined by the 1st byte in the spare area.
Samsung makes sure that the last page of every initial invalid block has
non-FFh data at the column address of 2,048.
...
"

As far as I can tell, this is the same for all Samsung MLC nand, and in
fact the samsung bsp for the processor used in our project (s3c6410)
actually contained a hack similar to this patch but less portable to
enable use of their NAND parts. I discovered this problem when trying to
use a Micron NAND which does not used this layout - I wish samsung would
put their stuff in main-line to avoid this type of problem.

Currently this patch causes all MLC nand with manufacturer codes from
Samsung and ST(Numonyx) to use this alternative location, since these
are the manufactures that I know of that use this layout.

Signed-off-by: Kevin Cernekee 
Signed-off-by: David Woodhouse

mtd: nand: extend NAND flash detection to new MLC chips

2010-05-14T00:54:44+00:00

Some of the newer MLC devices have a 6-byte ID sequence in which
several field definitions differ from older chips in a manner that is
not backward compatible.  For instance:

Samsung K9GAG08U0M (5-byte sequence): ec d5 14 b6 74
4th byte, bits 1:0 encode the page size: 0=1KiB, 1=2KiB, 2=4KiB, 3=8KiB
4th byte, bits 5:4 encode the block size: 0=64KiB, 1=128KiB, ...
4th byte, bit 6 encodes the OOB size: 0=8B/512B, 1=16B/512B

Samsung K9GAG08U0D (6-byte sequence): ec d5 94 29 34 41
4th byte, bits 1:0 encode the page size: 0=2KiB, 1=4KiB, 3=8KiB, 4=rsvd
4th byte, bits 7;5:4 encode the block size: 0=128KiB, 1=256KiB, ...
4th byte, bits 6;3:2 encode the OOB size: 1=128B/page, 2=218B/page

This patch uses the new 6-byte scheme if the following conditions are
all true:

1) The ID code wraps around after exactly 6 bytes

2) Manufacturer is Samsung

3) 6th byte is zero

The patch also extends the maximum OOB size from 128B to 256B.

Signed-off-by: Kevin Cernekee 
Signed-off-by: David Woodhouse

mtd: suppress warnings in inline_map_read()

2010-05-14T00:52:55+00:00

With gcc 4.4.3 -O2 on MIPS32:

drivers/mtd/chips/cfi_util.c: In function 'cfi_qry_present':
include/linux/mtd/map.h:390: warning: 'r' may be used uninitialized in this function
include/linux/mtd/map.h:375: note: 'r' was declared here
include/linux/mtd/map.h:390: warning: 'r' may be used uninitialized in this function
include/linux/mtd/map.h:375: note: 'r' was declared here

Signed-off-by: Kevin Cernekee 
Signed-off-by: Artem Bityutskiy 
Signed-off-by: David Woodhouse

mtd: map.h: add missing bug.h include

2010-05-14T00:52:32+00:00

Signed-off-by: Kevin Cernekee 
Signed-off-by: Artem Bityutskiy 
Signed-off-by: David Woodhouse

mtd: onenand: add new callback for bufferram read

2010-05-14T00:50:04+00:00

This patch adds a new callback for the underlying drivers, which is
called instead of accessing the buffer ram directly. This callback will
be used by Samsung OneNAND driver to implement DMA transfers on S5PC110
SoC.

Signed-off-by: Kyungmin Park 
Signed-off-by: Marek Szyprowski 
Signed-off-by: David Woodhouse

mtd: onenand: allocate verify buffer in the core

2010-05-14T00:49:48+00:00

This patch extends OneNAND core code with support for OneNAND verify
write check. This is done by allocating the buffer for verify read
directly from the core code.

Signed-off-by: Kyungmin Park 
Signed-off-by: Marek Szyprowski 
Signed-off-by: David Woodhouse

mtd: onenand: add support for chips with 4KiB page size

2010-05-14T00:49:21+00:00

This patch adds support for OneNAND chips that have 4KiB page size.

Signed-off-by: Kyungmin Park 
Signed-off-by: Marek Szyprowski 
Signed-off-by: David Woodhouse

mtd: chips: use common manufacturer codes in jedec_probe()

2010-05-14T00:48:58+00:00

Factor out old manufacturers and use the generic ones from cfi.h

Signed-off-by: Wolfram Sang 
Signed-off-by: David Woodhouse

mtd: cfi_probe: add support for SST 0x0701 vendorname

2010-05-14T00:08:11+00:00

SST 39VF160x and 39VF320x chips use vendorname id 0x0701 and alternative
unlock addresses. Add support for them in cfi_probe.c.

Signed-off-by: Guillaume LECERF 
Reviewed-by: Wolfram Sang 
Signed-off-by: David Woodhouse

mtd/nand/sh_flctl: Move function mtd_to_flctl to fix build failure

2010-05-12T22:24:23+00:00

This patch fixes a build failure[1] by simply moving the function mtd_to_flctl
beneath the definition of sh_flctl which it uses.

BF introduced by patch
'mtd/nand/sh_flctl: Replace the dangerous mtd_to_flctl macro' (67026418)

Signed-off-by: Peter Huewe 
Signed-off-by: David Woodhouse