linux-toradex.git/include/linux/nvhost.h, branch tegra-10.9.9 Linux kernel for Apalis and Colibri modules nvhost: Reimplement null kickoff functionality. 2010-08-19T13:09:18+00:00 Antoine Chauveau achauveau@nvidia.com 2010-08-11T07:55:17+00:00 d535635a14a7f5f82ab10456bd49e32c49285e00 For each channel submit where null kickoff is requested, we don't place the user's commands in the pushbuffer. All necessary context switches, syncpoint increments and waitbase increments do happen though. Bug 717235 Change-Id: I51c323729ea57993a5b52fb395ab90cb8608ee6b Reviewed-on: http://git-master/r/5091 Reviewed-by: Antoine Chauveau <achauveau@nvidia.com> Reviewed-by: Antti Hatala <ahatala@nvidia.com> Tested-by: Antti Hatala <ahatala@nvidia.com> 
For each channel submit where null kickoff is requested, we don't
place the user's commands in the pushbuffer. All necessary context
switches, syncpoint increments and waitbase increments do happen
though.

Bug 717235

Change-Id: I51c323729ea57993a5b52fb395ab90cb8608ee6b
Reviewed-on: http://git-master/r/5091
Reviewed-by: Antoine Chauveau <achauveau@nvidia.com>
Reviewed-by: Antti Hatala <ahatala@nvidia.com>
Tested-by: Antti Hatala <ahatala@nvidia.com>
tegra video: add driver for host1x hardware 2010-07-29T11:41:50+00:00 Andrew Howe ahowe@nvidia.com 2010-07-19T11:01:11+00:00 a91a0fdac15143e19335d837798133ad7dc22045 The graphics hardware modules on Tegra family of SOCs are accessed via the host1x dma and synchronization engine. This driver exposes an userspace interface for submitting command buffers to 2d, 3d, display and mpe hardware modules and accessing the module register apertures for exclusive use hardware modules. Additional features of the driver include: - interrupt-driven hardware module usage synchronization - automatic clock management for hw modules - hardware context switching for 3d registers Change-Id: I693582249597fd307526ff3c7e35889d37406017 Reviewed-on: http://git-master/r/4091 Reviewed-by: Janne Hellsten <jhellsten@nvidia.com> Tested-by: Janne Hellsten <jhellsten@nvidia.com> 
The graphics hardware modules on Tegra family of SOCs are accessed via
the host1x dma and synchronization engine. This driver exposes an
userspace interface for submitting command buffers to 2d, 3d, display
and mpe hardware modules and accessing the module register apertures
for exclusive use hardware modules.

Additional features of the driver include:
- interrupt-driven hardware module usage synchronization
- automatic clock management for hw modules
- hardware context switching for 3d registers

Change-Id: I693582249597fd307526ff3c7e35889d37406017
Reviewed-on: http://git-master/r/4091
Reviewed-by: Janne Hellsten <jhellsten@nvidia.com>
Tested-by: Janne Hellsten <jhellsten@nvidia.com>