linux-toradex.git/include/linux/pci-epf.h, branch v5.10-rc2

PCI: dwc: Fix dw_pcie_ep_raise_msix_irq() to get correct MSI-X table address

2020-04-02T16:57:10+00:00

commit beb4641a787d ("PCI: dwc: Add MSI-X callbacks handler"),
in order to raise MSI-X interrupt, obtained MSIX table address from
Base Address Register (BAR). However BAR only holds PCI address
programmed by the host whereas the MSI-X table should be in the local
memory.

Store the MSI-X table address (virtual address) as part of ->set_bar()
callback and use that to get the message address and message data
here.

Fixes: beb4641a787d ("PCI: dwc: Add MSI-X callbacks handler")
Signed-off-by: Kishon Vijay Abraham I 
Signed-off-by: Lorenzo Pieralisi

PCI: endpoint: Add notification for core init completion

2020-02-25T12:02:25+00:00

Add support to send notifications to EPF from EPC once the core
registers initialization is complete.

Signed-off-by: Vidya Sagar 
Signed-off-by: Lorenzo Pieralisi 
Acked-by: Kishon Vijay Abraham I

PCI: endpoint: Protect concurrent access to pci_epf_ops with mutex

2020-02-24T10:15:33+00:00

Protect concurrent access to pci_epf_ops with a mutex.

Signed-off-by: Kishon Vijay Abraham I 
Signed-off-by: Lorenzo Pieralisi

PCI: endpoint: Use notification chain mechanism to notify EPC events to EPF

2020-02-24T10:07:06+00:00

Use atomic_notifier_call_chain() to notify EPC events like linkup to EPF
driver instead of using linkup ops in EPF driver. This is in preparation
for adding proper locking mechanism to EPF ops. This will also enable to
add more events (in addition to linkup) in the future.

Signed-off-by: Kishon Vijay Abraham I 
Signed-off-by: Lorenzo Pieralisi 
Tested-by: Vidya Sagar

PCI: endpoint: Add support to specify alignment for buffers allocated to BARs

2019-04-15T12:24:02+00:00

The address that is allocated using pci_epf_alloc_space() is
directly written to the target address of the Inbound Address
Translation unit (ie the HW component implementing inbound address
decoding) on endpoint controllers.

Designware IP [1] has a configuration parameter (CX_ATU_MIN_REGION_SIZE
[2]) which has 64KB as default value and the lower 16 bits of the Base,
Limit and Target registers of the Inbound ATU are fixed to zero. If the
programmed memory address is not aligned to 64 KB boundary this causes
memory corruption.

Modify pci_epf_alloc_space() API to take alignment size as argument in
order to allocate buffers to be mapped to BARs with an alignment that
suits the platform where they are used.

Add an 'align' parameter to epc_features which can be used by platform
drivers to specify the BAR allocation alignment requirements and use
this while invoking pci_epf_alloc_space().

[1] "I/O and MEM Match Modes" section in DesignWare Cores PCI Express
     Controller Databook version 4.90a
[2]  http://www.ti.com/lit/ug/spruid7c/spruid7c.pdf

Signed-off-by: Kishon Vijay Abraham I 
Signed-off-by: Lorenzo Pieralisi

PCI: endpoint: Add MSI-X interfaces

2018-07-19T10:34:23+00:00

Add PCI_EPC_IRQ_MSIX type.

Add MSI-X callbacks signatures to the ops structure.

Add sysfs interface for set/get MSI-X capability maximum number.

Update documentation accordingly.

Signed-off-by: Gustavo Pimentel 
Signed-off-by: Lorenzo Pieralisi 
Acked-by: Kishon Vijay Abraham I

PCI: endpoint: Create configfs entry for each pci_epf_device_id table entry

2018-05-18T15:40:50+00:00

In order to be able to provide correct driver_data for pci_epf device,
a separate configfs entry for each pci_epf_device_id table entry in
pci_epf_driver is required.

Add support to create configfs entry for each pci_epf_device_id
table entry here.

Signed-off-by: Kishon Vijay Abraham I 
Signed-off-by: Lorenzo Pieralisi 
Tested-by: Gustavo Pimentel

PCI: endpoint: Simplify epc->ops->set_bar()/pci_epc_set_bar()

2018-04-03T11:23:38+00:00

Add barno and flags to struct epf_bar.
That way we can simplify epc->ops->set_bar()/pci_epc_set_bar()
by passing a struct *epf_bar instead of a whole lot of arguments.

This is needed so that epc->ops->set_bar() implementations can
modify BAR flags. Will be utilized in a succeeding patch.

Signed-off-by: Niklas Cassel 
Signed-off-by: Lorenzo Pieralisi 
Reviewed-by: Gustavo Pimentel 
Acked-by: Kishon Vijay Abraham I

PCI: Add SPDX GPL-2.0 to replace GPL v2 boilerplate

2018-01-28T21:48:29+00:00

Add SPDX GPL-2.0 to all PCI files that specified the GPL version 2 license.

Remove the boilerplate GPL version 2 language, relying on the assertion in
b24413180f56 ("License cleanup: add SPDX GPL-2.0 license identifier to
files with no license") that the SPDX identifier may be used instead of the
full boilerplate text.

Signed-off-by: Bjorn Helgaas 
Reviewed-by: Greg Kroah-Hartman

Merge branch 'pci/endpoint' into next

2017-09-07T18:24:11+00:00

* pci/endpoint:
  tools: PCI: Add a missing option help line
  misc: pci_endpoint_test: Enable/Disable MSI using module param
  misc: pci_endpoint_test: Avoid using hard-coded BAR sizes
  misc: pci_endpoint_test: Add support to not enable MSI interrupts
  misc: pci_endpoint_test: Add support to provide aligned buffer addresses
  misc: pci_endpoint_test: Add support for PCI_ENDPOINT_TEST regs to be mapped to any BAR
  PCI: designware-ep: Do not disable BARs during initialization
  PCI: dra7xx: Reset all BARs during initialization
  PCI: dwc: designware: Provide page_size to pci_epc_mem
  PCI: endpoint: Remove the ->remove() callback
  PCI: endpoint: Add support to poll early for host commands
  PCI: endpoint: Add support to use _any_ BAR to map PCI_ENDPOINT_TEST regs
  PCI: endpoint: Do not reset *command* inadvertently
  PCI: endpoint: Add "volatile" to pci_epf_test_reg
  PCI: endpoint: Add support for configurable page size
  PCI: endpoint: Make ->remove() callback optional
  PCI: endpoint: Add an API to get matching "pci_epf_device_id"
  PCI: endpoint: Use of_dma_configure() to set initial DMA mask