linux-toradex.git/include/linux/pci.h, branch v2.6.25-rc2

Change pci_raw_ops to pci_raw_read/write

2008-02-10T20:52:46+00:00

We want to allow different implementations of pci_raw_ops for standard
and extended config space on x86.  Rather than clutter generic code with
knowledge of this, we make pci_raw_ops private to x86 and use it to
implement the new raw interface -- raw_pci_read() and raw_pci_write().

Signed-off-by: Matthew Wilcox 
Signed-off-by: Linus Torvalds

iommu sg merging: PCI: add dma segment boundary support

2008-02-05T17:44:12+00:00

This adds PCI's accessor for segment_boundary_mask in device_dma_parameters.

The default segment_boundary is set to 0xffffffff, same to the block layer's
default value (and the scsi mid layer uses the same value).

Signed-off-by: FUJITA Tomonori 
Cc: James Bottomley 
Cc: Jens Axboe 
Cc: Greg KH 
Cc: Jeff Garzik 
Signed-off-by: Andrew Morton 
Signed-off-by: Linus Torvalds

iommu sg merging: PCI: add device_dma_parameters support

2008-02-05T17:44:10+00:00

This adds struct device_dma_parameters in struct pci_dev and properly
sets up a pointer in struct device.

The default max_segment_size is set to 64K, same to the block layer's
default value.

Signed-off-by: FUJITA Tomonori 
Mostly-acked-by: Jeff Garzik 
Cc: James Bottomley 
Acked-by: Jens Axboe 
Signed-off-by: Andrew Morton 
Signed-off-by: Linus Torvalds

Revert "PCI: PCIE ASPM support"

2008-02-02T19:32:01+00:00

This reverts commit 6c723d5bd89f03fc3ef627d50f89ade054d2ee3b.

It caused build errors on non-x86 platforms, config file confusion, and
even some boot errors on some x86-64 boxes.  All around, not quite ready
for prime-time :(

Cc: Shaohua Li 
Signed-off-by: Greg Kroah-Hartman

PCI: make pci_bus a struct device

2008-02-01T23:04:31+00:00

This moves the pci_bus class device to be a real struct device and at
the same time, place it in the device tree in the correct location.

Note, the old "bridge" symlink is now gone, but this was a non-standard
link and no userspace program used it.  If you need to determine the
device that the bus is on, follow the standard device symlink, or walk
up the device tree.


Signed-off-by: Greg Kroah-Hartman

PCI: fix codingstyle issues in include/linux/pci.h

2008-02-01T23:04:31+00:00

Fixes a number of coding style issues in pci.h.
It's a tad more readable now...

Signed-off-by: Greg Kroah-Hartman

PCI: PCIE ASPM support

2008-02-01T23:04:30+00:00

PCI Express ASPM defines a protocol for PCI Express components in the D0
state to reduce Link power by placing their Links into a low power state
and instructing the other end of the Link to do likewise. This
capability allows hardware-autonomous, dynamic Link power reduction
beyond what is achievable by software-only controlled power management.
However, The device should be configured by software appropriately.
Enabling ASPM will save power, but will introduce device latency.

This patch adds ASPM support in Linux. It introduces a global policy for
ASPM, a sysfs file /sys/module/pcie_aspm/parameters/policy can control
it. The interface can be used as a boot option too. Currently we have
below setting:
        -default, BIOS default setting
        -powersave, highest power saving mode, enable all available ASPM
state
and clock power management
        -performance, highest performance, disable ASPM and clock power
management
By default, the 'default' policy is used currently.

In my test, power difference between powersave mode and performance mode
is about 1.3w in a system with 3 PCIE links.

Signed-off-by: Shaohua Li 
Signed-off-by: Greg Kroah-Hartman

PCI: Remove pci_enable_device_bars()

2008-02-01T23:04:28+00:00

Now that all in-tree users are gone, this removes pci_enable_device_bars()
completely.

Signed-off-by: Benjamin Herrenschmidt 
Signed-off-by: Greg Kroah-Hartman

PCI: Add pci_enable_device_{io,mem} intefaces

2008-02-01T23:04:27+00:00

The pci_enable_device_bars() interface isn't well suited to PCI
because you can't actually enable/disable BARs individually on
a device. So for example, if a device has 2 memory BARs 0 and 1,
and one of them (let's say 1) has not been successfully allocated
by the firmware or the kernel, then enabling memory decoding
shouldn't be permitted for the entire device since it will decode
whatever random address is still in that BAR 1.

So a device must be either fully enabled for IO, for Memory, or
for both. Not on a per-BAR basis.

This provides two new functions, pci_enable_device_io() and
pci_enable_device_mem() to replace pci_enable_device_bars(). The
implementation internally builds a BAR mask in order to be able
to use existing arch infrastructure.

Signed-off-by: Benjamin Herrenschmidt 
Acked-by: Ivan Kokshaysky 
Signed-off-by: Greg Kroah-Hartman

PCI: Fix bus resource assignment on 32 bits with 64b resources

2008-02-01T23:04:25+00:00

The current pci_assign_unassigned_resources() code doesn't work properly
on 32 bits platforms with 64 bits resources. The main reason is the use
of unsigned long in various places instead of resource_size_t.

This is a pre-requisite for making powerpc use the generic code instead of
its own half-useful implementation.

Signed-off-by: Benjamin Herrenschmidt 
Signed-off-by: Greg Kroah-Hartman