linux-toradex.git/include/linux/pci.h, branch v3.3.5

PCI: Increase resource array mask bit size in pcim_iomap_regions()

2012-01-06T20:15:21+00:00

DEVICE_COUNT_RESOURCE will be bigger than 16 when SRIOV supported is enabled.

Let them pass with int just like pci_enable_resources().

Signed-off-by: Yinghai Lu 
Signed-off-by: Jesse Barnes

PCI: DEVICE_COUNT_RESOURCE should be equal to PCI_NUM_RESOURCES

2012-01-06T20:15:14+00:00

Save some bytes for device resource array.

Signed-off-by: Yinghai Lu 
Signed-off-by: Jesse Barnes

PCI: remove pci_create_bus()

2012-01-06T20:11:15+00:00

All users of pci_create_bus() have been converted to pci_create_root_bus(),
so remove it.

Signed-off-by: Bjorn Helgaas 
Signed-off-by: Jesse Barnes

PCI: convert pci_scan_bus() to use pci_create_root_bus()

2012-01-06T20:10:53+00:00

I plan to deprecate pci_scan_bus_parented(), so use pci_create_root_bus()
directly instead.  pci_scan_bus() itself will be removed as soon as all
callers are gone, so this is just an interim step.

v2: export pci_scan_bus

Signed-off-by: Bjorn Helgaas 
Signed-off-by: Jesse Barnes

PCI: add pci_scan_root_bus() that accepts resource list

2012-01-06T20:10:52+00:00

"Early" and "header" quirks often use incorrect bus resources because they
see the default resources assigned by pci_create_bus(), before the
architecture fixes them up (typically in pcibios_fixup_bus()).  Regions
reserved by these quirks end up with the wrong parents.

Here's the standard path for scanning a PCI root bus:

  pci_scan_bus or pci_scan_bus_parented
    pci_create_bus                     <-- A create with default resources
    pci_scan_child_bus
      pci_scan_slot
        pci_scan_single_device
          pci_scan_device
            pci_setup_device
              pci_fixup_device(early)  <-- B
          pci_device_add
            pci_fixup_device(header)   <-- C
      pcibios_fixup_bus                <-- D fill in correct resources

Early and header quirks at B and C use the default (incorrect) root bus
resources rather than those filled in at D.

This patch adds a new pci_scan_root_bus() function that sets the bus
resources correctly from a supplied list of resources.

I intend to remove pci_scan_bus() and pci_scan_bus_parented() after
fixing all callers.

Signed-off-by: Bjorn Helgaas 
Signed-off-by: Jesse Barnes

PCI: add pci_create_root_bus() that accepts resource list

2012-01-06T20:10:51+00:00

pci_create_bus() assigns ioport_resource and iomem_resource as the default
bus resources, i.e., the entire address space.  Architectures fix these
later, typically in pcibios_fixup_bus() or after pci_scan_bus_parented()
returns, but code that runs in the interim sees incorrect resource
information.

This patch adds a new pci_create_root_bus() that sets the bus resources
correctly from a supplied list of resources.

I intend to remove pci_create_bus() after changing all callers.

Based on original patch by Deng-Cheng Zhu.

Reference: http://www.spinics.net/lists/mips/msg41654.html
Reference: https://lkml.org/lkml/2011/8/26/88
Signed-off-by: Deng-Cheng Zhu 
Signed-off-by: Bjorn Helgaas 
Signed-off-by: Jesse Barnes

PCI: add helpers for building PCI bus resource lists

2012-01-06T20:10:50+00:00

We'd like to supply a list of resources when we create a new PCI bus,
e.g., the root bus under a PCI host bridge.  These are helpers for
constructing that list.

These are exported because the plan is to replace this exported interface:
    pci_scan_bus_parented()
with this one:
    pci_add_resource(resources, ...)
    pci_scan_root_bus(..., resources)

Signed-off-by: Bjorn Helgaas 
Signed-off-by: Jesse Barnes

PCI: Pull PCI 'latency timer' setup up into the core

2012-01-06T20:10:42+00:00

The 'latency timer' of PCI devices, both Type 0 and Type 1,
is setup in architecture-specific code [see: 'pcibios_set_master()'].
There are two approaches being taken by all the architectures - check
if the 'latency timer' is currently set between 16 and 255 and if not
bring it within bounds, or, do nothing (and then there is the
gratuitously different PA-RISC implementation).

There is nothing architecture-specific about PCI's 'latency timer' so
this patch pulls its setup functionality up into the PCI core by
creating a generic 'pcibios_set_master()' function using the '__weak'
attribute which can be used by all architectures as a default which,
if necessary, can then be over-ridden by architecture-specific code.

No functional change.

Signed-off-by: Myron Stowe 
Signed-off-by: Jesse Barnes

PCI: add declaration for pcibios_set_master() to pci core

2012-01-06T20:10:35+00:00

Currently, pcibios_set_master() is implemented in architecture-
specific code.  There is nothing architecture-specific about PCI's
'latency timer'.

This patch adds a declaration for pcibios_set_master() to PCI's core
in preperation for pulling the function itself up into the core.
Without the addition of this declaration, subsequent patches that
remove inline definitions of pcibios_set_master() would be removing
the only declaration of such.

No functional change.

Signed-off-by: Myron Stowe 
Signed-off-by: Jesse Barnes

PCI: Introduce INTx check & mask API

2012-01-06T20:10:34+00:00

These new PCI services allow to probe for 2.3-compliant INTx masking
support and then use the feature from PCI interrupt handlers. The
services are properly synchronized with concurrent config space access
via sysfs or on device reset.

This enables generic PCI device drivers like uio_pci_generic or KVM's
device assignment to implement the necessary kernel-side IRQ handling
without any knowledge about device-specific interrupt status and control
registers.

Acked-by: Michael S. Tsirkin 
Signed-off-by: Jan Kiszka 
Signed-off-by: Jesse Barnes