Signed-off-by: David Howells <dhowells@redhat.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Michael Kerrisk <mtk.manpages@gmail.com> Acked-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com> Acked-by: Dave Jones <davej@redhat.com>
* pci/trivial: PCI: Drop duplicate const in DECLARE_PCI_FIXUP_SECTION PCI: Drop bogus default from ARCH_SUPPORTS_MSI PCI: cpqphp: Remove unreachable path PCI: Remove bus number resource debug messages PCI/AER: Print completion message at KERN_INFO to match starting message PCI: Fix drivers/pci/pci.c kernel-doc warnings
* pci/stephen-const: make drivers with pci error handlers const scsi: make pci error handlers const netdev: make pci_error_handlers const PCI: Make pci_error_handlers const
* pci/gavin-window-alignment: powerpc/powernv: I/O and memory alignment for P2P bridges powerpc/PCI: Override pcibios_window_alignment() PCI: Refactor pbus_size_mem() PCI: Align P2P windows using pcibios_window_alignment() PCI: Add weak pcibios_window_alignment() interface
This patch implements a weak function to return the default I/O or memory window alignment for a P2P bridge. By default, I/O windows are aligned to 4KiB or 1KiB and memory windows are aligned to 4MiB. Some platforms, e.g., powernv, have special alignment requirements and can override pcibios_window_alignment(). [bhelgaas: changelog] Signed-off-by: Gavin Shan <shangw@linux.vnet.ibm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
It's redundant and makes sparse complain about it. Signed-off-by: Mathias Krause <minipli@googlemail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Since pci_error_handlers is just a function table make it const. Signed-off-by: Stephen Hemminger <shemminger@vyatta.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Linas Vepstas <linasvepstas@gmail.com>
* pci/bjorn-cleanup-remove: PCI: Remove unused pci_dev_b() sgi-agp: Use list_for_each_entry() for bus->devices traversal parisc/PCI: Use list_for_each_entry() for bus->devices traversal parisc/PCI: Enable PERR/SERR on all devices frv/PCI: Use list_for_each_entry() for bus->devices traversal PCI: Leave normal LIST_POISON in deleted list entries PCI: Rename local variables to conventional names PCI: Remove unused, commented-out, code PCI: Stop and remove devices in one pass PCI: Fold stop and remove helpers into their callers PCI: Use list_for_each_entry() for bus->devices traversal PCI: Remove pci_stop_and_remove_behind_bridge() PCI: Don't export stop_bus_device and remove_bus_device interfaces pcmcia: Use common pci_stop_and_remove_bus_device() PCI: acpiphp: Use common pci_stop_and_remove_bus_device() PCI: acpiphp: Stop disabling bridges on remove
* pci/bjorn-find-next-ext-cap: PCI: Add Vendor-Specific Extended Capability header info PCI: Add pci_find_next_ext_capability() Conflicts: drivers/pci/pci.c
The PCI Express Capability (PCIe spec r3.0, sec 7.8) comes in two versions, v1 and v2. In v1 Capability structures (PCIe spec r1.0 and r1.1), some fields are optional, so the structure size depends on the device type. This patch adds functions to access this capability so drivers don't have to be aware of the differences between v1 and v2. Note that these new functions apply only to the "PCI Express Capability," not to any of the other "PCI Express Extended Capabilities" (AER, VC, ACS, MFVC, etc.) Function pcie_capability_read_word/dword() reads the PCIe Capabilities register and returns the value in the reference parameter "val". If the PCIe Capabilities register is not implemented on the PCIe device, "val" is set to 0. Function pcie_capability_write_word/dword() writes the value to the specified PCIe Capability register. Function pcie_capability_clear_and_set_word/dword() sets and/or clears bits of a PCIe Capability register. [bhelgaas: changelog, drop "pci_" prefixes, don't export pcie_capability_reg_implemented()] Signed-off-by: Jiang Liu <jiang.liu@huawei.com> Signed-off-by: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>