linux-toradex.git/include/linux/pci_regs.h, branch v2.6.30.5

PCI: only save/restore existent registers in the PCIe capability

2009-04-22T22:59:41+00:00

PCIe 1.1 base neither requires the endpoint to implement the entire
PCIe capability structure nor specifies default values of registers
that are not implemented by the device. So we only save and restore
registers that must be implemented by different device types if the
device PCIe capability version is 1.

PCIe 1.1 Capability Structure Expansion ECN and PCIe 2.0 requires
all registers in the PCIe capability to be either implemented or
hardwired to 0. Their PCIe capability version is 2.

Signed-off-by: Yu Zhao 
Signed-off-by: Jesse Barnes

PCI: save and restore PCIe 2.0 registers

2009-03-26T23:02:30+00:00

PCIe 2.0 defines several new registers (Device Control 2, Link Control 2,
and Slot Control 2). Save and retore them in pci_save_pcie_state() and
pci_restore_pcie_state().

Signed-off-by: Yu Zhao 
Signed-off-by: Jesse Barnes

PCI: initialize and release SR-IOV capability

2009-03-20T17:48:22+00:00

If a device has the SR-IOV capability, initialize it (set the ARI
Capable Hierarchy in the lowest numbered PF if necessary; calculate
the System Page Size for the VF MMIO, probe the VF Offset, Stride
and BARs). A lock for the VF bus allocation is also initialized if
a PF is the lowest numbered PF.

Reviewed-by: Matthew Wilcox 
Signed-off-by: Yu Zhao 
Signed-off-by: Jesse Barnes

PCI: fix incorrect mask of PM No_Soft_Reset bit

2009-03-20T17:48:08+00:00

Reviewed-by: Matthew Wilcox 
Signed-off-by: Yu Zhao 
Signed-off-by: Jesse Barnes

PCI: pciehp: cleanup register and field definitions

2009-01-07T19:13:22+00:00

Clean up register definitions related to PCI Express Hot plug.

  - Add register definitions into include/linux/pci_regs.h, and use
    them instead of pciehp's locally definied register definitions.
  - Remove pciehp's locally defined register definitions
  - Remove unused register definitions in pciehp.
  - Some minor cleanups.

Signed-off-by: Kenji Kaneshige 
Signed-off-by: Jesse Barnes

PCI: add PCI Advanced Feature Capability defines

2009-01-07T19:12:24+00:00

PCI Advanced Features Capability is introduced by "Conventional PCI
Advanced Caps ECN" (can be downloaded in pcisig.com).  Add defines for
the various AF capabilities, including function level reset (FLR).

Reviewed-by: Matthew Wilcox 
Signed-off-by: Sheng Yang 
Signed-off-by: Jesse Barnes

PCI: add support for function level reset

2008-10-22T23:42:35+00:00

Sometimes, it's necessary to enable software's ability to quiesce and
reset endpoint hardware with function-level granularity, so provide
support for it.

The patch implement Function Level Reset(FLR) feature following PCI-e
spec. And this is the first step. We would add more generic method, like
D0/D3, to allow more devices support this function.

The patch contains two functions. pcie_reset_function() is the new
driver API, and, contains some action to quiesce a device.  The other
function is a helper:  pcie_execute_reset_function() just executes the
reset for a particular device function.

Current the usage model is in KVM. Function reset is necessary for
assigning device to a guest, or moving it between partitions.

For Function Level Reset(FLR), please refer to PCI Express spec chapter
6.6.2.

Signed-off-by: Sheng Yang 
Signed-off-by: Matthew Wilcox 
Signed-off-by: Jesse Barnes

PCI: support PCIe ARI capability

2008-10-20T17:54:32+00:00

This patch adds support for PCI Express Alternative Routing-ID
Interpretation (ARI) capability.

The ARI capability extends the Function Number field of the PCI Express
Endpoint by reusing the Device Number which is otherwise hardwired to 0.
With ARI, an Endpoint can have up to 256 functions.

Signed-off-by: Yu Zhao 
Signed-off-by: Jesse Barnes

PCI: disable ASPM on pre-1.1 PCIe devices

2008-07-28T21:56:57+00:00

Disable ASPM on pre-1.1 PCIe devices, as many of them don't implement it
correctly.

Tested-by: Jack Howarth 
Signed-off-by: Shaohua Li 
Signed-off-by: Jesse Barnes

PCI: Simplify PCI device PM code

2008-07-07T23:26:50+00:00

If the offset of PCI device's PM capability in its configuration space,
the mask of states that the device supports PME# from and the D1 and D2
support bits are cached in the corresponding struct pci_dev, the PCI
device PM code can be simplified quite a bit.

Signed-off-by: Rafael J. Wysocki 
Signed-off-by: Jesse Barnes