linux-toradex.git/include/linux/phy.h, branch v4.16-rc4

phy: add helpers for setting/clearing bits in PHY registers

2018-01-16T17:25:10+00:00

Based on the recent introduction of phy_modify add helpers for setting
and clearing bits in PHY registers.

Signed-off-by: Heiner Kallweit 
Signed-off-by: David S. Miller

net: phy: remove parameter new_link from phy_mac_interrupt()

2018-01-15T18:45:03+00:00

I see two issues with parameter new_link:

1. It's not needed. See also phy_interrupt(), works w/o this parameter.
   phy_mac_interrupt sets the state to PHY_CHANGELINK and triggers the
   state machine which then calls phy_read_status. And phy_read_status
   updates the link state.

2. phy_mac_interrupt is used in interrupt context and getting the link
   state may sleep (at least when having to access the PHY registers
   via MDIO bus).

So let's remove it.

Signed-off-by: Heiner Kallweit 
Reviewed-by: Florian Fainelli 
Tested-by: Florian Fainelli 
Signed-off-by: David S. Miller

net: phy: add phy_modify() accessor

2018-01-03T16:00:23+00:00

Add phy_modify() convenience accessor to complement the mdiobus
counterpart.

Signed-off-by: Russell King 
Reviewed-by: Andrew Lunn 
Signed-off-by: David S. Miller

net: phy: add paged phy register accessors

2018-01-03T16:00:23+00:00

Add a set of paged phy register accessors which are inherently safe in
their design against other accesses interfering with the paged access.

Signed-off-by: Russell King 
Reviewed-by: Andrew Lunn 
Signed-off-by: David S. Miller

net: phy: add unlocked accessors

2018-01-03T16:00:22+00:00

Add unlocked versions of the bus accessors, which allows access to the
bus with all the tracing. These accessors validate that the bus mutex
is held, which is a basic requirement for all mii bus accesses.

Also added is a read-modify-write unlocked accessor with the same
locking requirements.

Signed-off-by: Russell King 
Reviewed-by: Andrew Lunn 
Signed-off-by: David S. Miller

net: phy: add helper to convert negotiation result to phy settings

2018-01-02T20:00:50+00:00

Add a helper to convert the result of the autonegotiation advertisment
into the PHYs speed and duplex settings.  If the result is full duplex,
also extract the pause mode settings from the link partner advertisment.

Signed-off-by: Russell King 
Reviewed-by: Andrew Lunn 
Signed-off-by: David S. Miller

net: phy: marvell10g: add MDI swap reporting

2018-01-02T20:00:49+00:00

Add reporting of the MDI swap to the Marvell 10G PHY driver by providing
a generic implementation for the standard 10GBASE-T pair swap register
and polarity register.  We also support reading the MDI swap status for
1G and below from a PCS register.

Signed-off-by: Russell King 
Reviewed-by: Andrew Lunn 
Signed-off-by: David S. Miller

phylib: add reset after clk enable support

2017-12-13T16:22:53+00:00

Some PHYs need the refclk to be a continuous clock. Therefore they don't
allow turning it off and on again during operation. Nonetheless such a
clock switching is performed by some ETH drivers (namely FEC [1]) for
power saving reasons. An example for an affected PHY is the
SMSC/Microchip LAN8720 in "REF_CLK In Mode".

In order to provide a uniform method to overcome this problem this patch
adds a new phy_driver flag (PHY_RST_AFTER_CLK_EN) and corresponding
function phy_reset_after_clk_enable() to the phylib. These should be
used to trigger reset of the PHY after the refclk is switched on again.

[1] commit e8fcfcd5684a ("net: fec: optimize the clock management to save power")

Signed-off-by: Richard Leitner 
Reviewed-by: Andrew Lunn 
Signed-off-by: David S. Miller

phylib: Add device reset GPIO support

2017-12-05T17:51:19+00:00

The PHY devices sometimes do have their reset signal (maybe even power
supply?) tied to some GPIO and sometimes it also does happen that a boot
loader does not leave it deasserted. So far this issue has been attacked
from (as I believe) a wrong angle: by teaching the MAC driver to manipulate
the GPIO in question; that solution, when applied to the device trees, led
to adding the PHY reset GPIO properties to the MAC device node, with one
exception: Cadence MACB driver which could handle the "reset-gpios" prop
in a PHY device subnode. I believe that the correct approach is to teach
the 'phylib' to get the MDIO device reset GPIO from the device tree node
corresponding to this device -- which this patch is doing...

Note that I had to modify the AT803x PHY driver as it would stop working
otherwise -- it made use of the reset GPIO for its own purposes...

Signed-off-by: Sergei Shtylyov 
Acked-by: Rob Herring 
[geert: Propagate actual errors from fwnode_get_named_gpiod()]
[geert: Avoid destroying initial setup]
[geert: Consolidate GPIO descriptor acquiring code]
Signed-off-by: Geert Uytterhoeven 
Tested-by: Richard Leitner 
Signed-off-by: David S. Miller

phy: add phy_interface_mode_is_8023z() helper

2017-12-05T16:16:17+00:00

Add and use phy_interface_mode_is_8023z() helper to identify the
interface modes that use 802.3z negotiation.  Use it in phylink's
phylink_mac_an_restart().

Signed-off-by: Russell King 
Reviewed-by: Florian Fainelli 
Signed-off-by: David S. Miller