linux-toradex.git/include/linux/pxa2xx_ssp.h, branch v4.9.122

spi: pxa2xx: Default thresholds to PXA configuration

2016-09-12T19:01:43+00:00

Most of the devices in the supported list have PXA configuration of FIFO. In
particularly Intel Medfield and Merrifield have bigger FIFO, than it's defined
for CE4100.

Split CE4100 in the similar way how it was done for Intel Quark, i.e. prefix
definitions by CE4100 and append necessary pieces of code to switch case
conditions.

We are on safe side since those bits are ignored on all LPSS IPs.

Signed-off-by: Andy Shevchenko 
Reviewed-by: Jarkko Nikula 
Signed-off-by: Mark Brown

spi: pxa2xx: Add support for both chip selects on Intel Braswell

2016-02-09T19:01:11+00:00

Intel Braswell LPSS SPI controller actually has two chip selects and there
is no capabilities register where this could be found out. These two chip
selects are controlled by bits which are in slightly differrent location
than Broxton has.

Braswell Windows driver also starts chip select (ACPI DeviceSelection)
numbering from 1 so translate it to be suitable for Linux as well.

Signed-off-by: Mika Westerberg 
Reviewed-by: Jarkko Nikula 
Reviewed-by: Andy Shevchenko 
Signed-off-by: Mark Brown

spi: pxa2xx: Add support for Intel Broxton

2015-10-30T02:18:05+00:00

LPSS SPI in Intel Broxton is otherwise the same than in Intel Sunrisepoint
but it supports up to four chip selects per port and has different FIFO
thresholds. Patch adds support for two Broxton SoC variants.

Signed-off-by: Jarkko Nikula 
Signed-off-by: Mark Brown

spi: pxa2xx: Add support for Intel Sunrisepoint

2015-07-31T18:13:33+00:00

Major difference in LPSS SPI between Intel Sunrisepoint PCH and earlier
platforms is an integrated DMA (iDMA) engine. iDMA is an IP that is private
for each LPSS host controller (UART/SPI/I2C). Other differences are private
register space offset, a few private registers that are in different
location and FIFO thresholds.

Intel Sunrisepoint LPSS SPI and iDMA devices are probed and registered in
MFD layer as platform devices. Here these compound devices are detected by
matching against known PCI IDs. This allows us to share
pxa2xx_spi_acpi_get_pdata() for setting up the platform data instead of
duplicating it in MFD part.

This patch adds configuration for Intel Sunrisepoint LPSS SPI, above
detection and DMA filter function that picks the DMA channel only from an
associated iDMA block.

Signed-off-by: Jarkko Nikula 
Signed-off-by: Mark Brown

spi: pxa2xx: Prepare for new Intel LPSS SPI type

2015-06-05T10:40:45+00:00

Some of the Intel LPSS SPI properties will be different in upcoming
platforms compared to existing Lynxpoint and BayTrail/Braswell. LPSS SPI
private registers will be at different offset and there will be changes in
individual registers and default FIFO thresholds too.

Add configuration for these differences and use them in runtime based on
LPSS SSP type. With this change private registers offset autodetection
becomes needless.

Signed-off-by: Jarkko Nikula 
Signed-off-by: Mark Brown

spi: pxa2xx: Differentiate Intel LPSS types

2015-06-05T10:40:45+00:00

Intel LPSS SPI properties differ between between platforms. Now private
registers offset 0x400 or 0x800 is autodetected but there is need to
support also other offset and handle a few other differences.

Prepare for that by splitting the LPSS_SSP type into compatible hardware
types and set it now based on PCI or ACPI ID. That type will be used to set
properties that differ between current and upcoming platforms.

Signed-off-by: Jarkko Nikula 
Signed-off-by: Mark Brown

spi: pxa2xx: Add definition for Intel Quark DDS_RATE register

2014-12-22T20:17:23+00:00

Intel Quark DDS_RATE register is defined only in register access macro. Add
a definition for it to common SSP register definitions for preparing to
cleanup those macros.

Signed-off-by: Jarkko Nikula 
Signed-off-by: Mark Brown

spi: spi-pxa2xx: SPI support for Intel Quark X1000

2014-11-26T18:07:45+00:00

There are two SPI controllers exported by PCI subsystem for Intel Quark X1000.
The SPI memory mapped I/O registers supported by Quark are different from
the current implementation, and Quark only supports the registers of 'SSCR0',
'SSCR1', 'SSSR', 'SSDR', and 'DDS_RATE'. This patch is to enable the SPI for
Intel Quark X1000.

This piece of work is derived from Dan O'Donovan's initial work for Intel Quark
X1000 SPI enabling.

Reviewed-by: Andy Shevchenko 
Acked-by: Mika Westerberg 
Signed-off-by: Weike Chen 
Signed-off-by: Mark Brown

ARM: pxa: fix pxa_ssp_* declarations

2014-03-21T17:26:03+00:00

The functions declared in include/linux/pxa2xx_ssp.h are
defined in plat-pxa/ssp.c, which can also be built for
PLAT_MMP, but may be disabled there. This can lead to
both unresolved symbols at link time and to duplicate
symbols at compile time for random configurations.

Changing the #ifdef in the header file to match the
Kconfig symbol that decides if the file is built solves
both problems.

Signed-off-by: Arnd Bergmann 
Cc: Eric Miao 
Cc: Russell King 
Cc: Haojian Zhuang 
Cc: Daniel Mack

ARM: pxa: ssp: add pxa_ssp_request_of()

2013-08-14T18:54:30+00:00

Add a function to lookup ssp devices from device tree. This way, users
can reference the ssp devices in order to register to them.

Signed-off-by: Daniel Mack 
Acked-by: Haojian Zhuang 
Signed-off-by: Mark Brown