linux-toradex.git/include/linux/sh_intc.h, branch v2.6.34-rc3

sh: extend INTC with force_disable

2010-02-16T04:38:56+00:00

Extend the shared INTC code with force_disable support to
allow keeping mask bits statically disabled. Needed for
SDHI support to mask out unsupported interrupt sources.

Signed-off-by: Magnus Damm 
Signed-off-by: Paul Mundt

sh: extend INTC with force_enable

2010-02-09T09:23:58+00:00

Extend the shared INTC code with force_enable support to
allow keeping mask bits statically enabled. Needed by
upcoming INTC SDHI patches that mux together a bunch of
vectors to a single linux interrupt which is masked by
a priority register, but needs individual mask bits
constantly enabled.

Signed-off-by: Magnus Damm 
Signed-off-by: Paul Mundt

sh: extend INTC with struct intc_hw_desc

2010-02-09T09:23:57+00:00

This patch updates the INTC code by moving all vectors,
groups and registers from struct intc_desc to struct
intc_hw_desc.

The idea is that INTC tables should go from using the
macro(s) DECLARE_INTC_DESC..() only to using struct
intc_desc with name and hw initialized using the macro
INTC_HW_DESC(). This move makes it easy to initialize
an extended struct intc_desc in the future.

Signed-off-by: Magnus Damm 
Signed-off-by: Paul Mundt

sh: intc: Handle legacy IRQ reservation in vector map.

2009-11-02T06:43:20+00:00

Different CPUs will have different starting vectors, with varying
amounts of reserved or unusable vector space prior to the first slot.
This introduces a legacy vector reservation system that inserts itself in
between the CPU vector map registration and the platform specific IRQ
setup. This works fine in practice as the only new vectors that boards
need to establish on their own should be dynamically allocated rather
than arbitrarily assigned. As a plus, this also makes all of the
converted platforms sparseirq ready.

Signed-off-by: Paul Mundt

sh: intc: Make ack_regs generally available.

2009-10-27T02:36:43+00:00

Currently this is ifdef'ed under SH-3 and SH-4A, but there are other CPUs
that will need this as well. Given the size of the existing data
structures, this doesn't cause any additional cacheline utilization for
the existing users, so has no direct impact on the data structures.

Signed-off-by: Paul Mundt

sh: Simplify "multi-evt" interrupt handling.

2009-08-24T10:52:38+00:00

This patch changes the way in which "multi-evt" interrups are handled.
The intc_evt2irq_table and related intc_evt2irq() have been removed and
the "redirecting" handler is installed for the coupled interrupts.

Thanks to that the do_IRQ() function don't have to use another level
of indirection for all the interrupts...

Signed-off-by: Pawel Moll 
Signed-off-by: Stuart Menefy 
Signed-off-by: Paul Mundt

sh: multiple vectors per irq - base

2009-02-27T07:53:50+00:00

Instead of keeping the single vector -> single linux irq mapping
we extend the intc code to support merging of vectors to a single
linux irq. This helps processors such as sh7750, sh7780 and sh7785
which have more vectors than masking ability. With this patch in
place we can modify the intc tables to use one irq per maskable
irq source. Please note the following:

 - If multiple vectors share the same enum then only the
   first vector will be available as a linux irq.

 - Drivers may need to be rewritten to get pending irq
   source from the hardware block instead of irq number.

This patch together with the sh7785 specific intc tables solves
DMA controller irq issues related to buggy interrupt masking.

Reported-by: Yoshihiro Shimoda 
Signed-off-by: Magnus Damm 
Signed-off-by: Paul Mundt

sh: Move the shared INTC code out to drivers/sh/

2008-10-01T07:13:54+00:00

The INTC code will be re-used across different architectures, so move
this out to drivers/sh/ and include/linux/sh_intc.h respectively.

Signed-off-by: Paul Mundt