linux-toradex.git/include/linux/soc/qcom, branch v5.17-rc1 Linux kernel for Apalis and Colibri modules soc: qcom: llcc: Add configuration data for SM8350 2021-12-21T01:10:09+00:00 Konrad Dybcio konrad.dybcio@somainline.org 2021-11-21T00:20:46+00:00 6fc61c39ee1adb5f4115d288c876772fcd8b6979 Add LLCC configuration data for SM8350 SoC. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211121002050.36977-2-konrad.dybcio@somainline.org 
Add LLCC configuration data for SM8350 SoC.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211121002050.36977-2-konrad.dybcio@somainline.org
Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux 2021-11-04T04:18:44+00:00 Linus Torvalds torvalds@linux-foundation.org 2021-11-04T04:18:44+00:00 7ddb58cb0ecae8e8b6181d736a87667cc9ab8389 Pull clk updates from Stephen Boyd: "The usual collection of clk driver updates and new driver additions. In terms of lines it's mainly Qualcomm and Mediatek code, supporting various SoCs and their multitude of clk controllers. New Drivers: - GCC and RPMcc support for Qualcomm QCM2290 SoCs - GCC support for Qualcomm MSM8994/MSM8992 SoCs - LPASSCC and CAMCC support for Qualcomm SC7280 SoCs - Support for Mediatek MT8195 SoCs - Initial clock driver for the Exynos850 SoC - Add i.MX8ULP clock driver and related bindings Updates: - Clock power management for new SAMA7G5 SoC - Updates to the master clock driver and sam9x60-pll to be able to use cpufreq-dt driver and avoid overclocking of CPU and MCK0 domains while changing the frequency via DVFS - Use ARRAY_SIZE in qcom clk drivers - Remove some impractical fallback parent names in qcom clk drivers - Make Mediatek clk drivers tristate - Refactoring of the CPU clock code and conversion of Samsung Exynos5433 CPU clock driver to the platform driver - A few conversions to devm_platform_ioremap_resource() - Updates of the Samsung Kconfig help text - Update video path realted clocks for Amlogic meson8 - Add SPI Multi I/O Bus and SDHI clocks and resets on Renesas RZ/G2L - Add SPI Multi I/O Bus (RPC) clocks on Renesas R-Car V3U - Add MediaLB clocks on Renesas R-Car H3, M3-W/W+, and M3-N - Remove unused helpers from i.MX specific clock header - Rework all i.MX clk based helpers to use clk_hw based ones - Rework i.MX gate/mux/divider wrappers - Rework imx_clk_hw_composite and imx_clk_hw_pll14xx wrappers - Update i.MX pllv4 and composite clocks to support i.MX8ULP - Disable i.MX7ULP composite clock during initialization - Add CLK_SET_RATE_NO_REPARENT flag to the i.MX7ULP composite - Disable the i.MX pfd when set pfdv2 clock rate - Add support for i.MX8ULP in pfdv2 - Add the pcc reset controller support on i.MX8ULP - Fix the build break when clk-imx8ulp is built as module - Move csi_sel mux to correct base register in i.MX6UL clock drivr - Fix csi clk gate register in i.MX6UL clock driver - Fix build bug making CLK_IMX8ULP select MXC_CLK - Add TPU (PWM), and Z (Cortex-A76) clocks on Renesas R-Car V3U - Add Ethernet clocks on Renesas RZ/G2L - Move Rockchip to use module_platform_probe - Enable usage of Coresight related clocks on Rockchip rk3399" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (170 commits) clk: use clk_core_get_rate_recalc() in clk_rate_get() clk: at91: sama7g5: set low limit for mck0 at 32KHz clk: at91: sama7g5: remove prescaler part of master clock clk: at91: clk-master: add notifier for divider clk: at91: clk-sam9x60-pll: add notifier for div part of PLL clk: at91: clk-master: fix prescaler logic clk: at91: clk-master: mask mckr against layout->mask clk: at91: clk-master: check if div or pres is zero clk: at91: sam9x60-pll: use DIV_ROUND_CLOSEST_ULL clk: at91: pmc: add sama7g5 to the list of available pmcs clk: at91: clk-master: improve readability by using local variables clk: at91: clk-master: add register definition for sama7g5's master clock clk: at91: sama7g5: add securam's peripheral clock clk: at91: pmc: execute suspend/resume only for backup mode clk: at91: re-factor clocks suspend/resume clk: ux500: Add driver for the reset portions of PRCC dt-bindings: clock: u8500: Rewrite in YAML and extend clk: composite: Use rate_ops.determine_rate when also a mux is available clk: samsung: describe drivers in Kconfig clk: samsung: exynos5433: update apollo and atlas clock probing ... 
Pull clk updates from Stephen Boyd:
 "The usual collection of clk driver updates and new driver additions.
  In terms of lines it's mainly Qualcomm and Mediatek code, supporting
  various SoCs and their multitude of clk controllers.

  New Drivers:
   - GCC and RPMcc support for Qualcomm QCM2290 SoCs
   - GCC support for Qualcomm MSM8994/MSM8992 SoCs
   - LPASSCC and CAMCC support for Qualcomm SC7280 SoCs
   - Support for Mediatek MT8195 SoCs
   - Initial clock driver for the Exynos850 SoC
   - Add i.MX8ULP clock driver and related bindings

  Updates:
   - Clock power management for new SAMA7G5 SoC
   - Updates to the master clock driver and sam9x60-pll to be able to
     use cpufreq-dt driver and avoid overclocking of CPU and MCK0
     domains while changing the frequency via DVFS
   - Use ARRAY_SIZE in qcom clk drivers
   - Remove some impractical fallback parent names in qcom clk drivers
   - Make Mediatek clk drivers tristate
   - Refactoring of the CPU clock code and conversion of Samsung
     Exynos5433 CPU clock driver to the platform driver
   - A few conversions to devm_platform_ioremap_resource()
   - Updates of the Samsung Kconfig help text
   - Update video path realted clocks for Amlogic meson8
   - Add SPI Multi I/O Bus and SDHI clocks and resets on Renesas RZ/G2L
   - Add SPI Multi I/O Bus (RPC) clocks on Renesas R-Car V3U
   - Add MediaLB clocks on Renesas R-Car H3, M3-W/W+, and M3-N
   - Remove unused helpers from i.MX specific clock header
   - Rework all i.MX clk based helpers to use clk_hw based ones
   - Rework i.MX gate/mux/divider wrappers
   - Rework imx_clk_hw_composite and imx_clk_hw_pll14xx wrappers
   - Update i.MX pllv4 and composite clocks to support i.MX8ULP
   - Disable i.MX7ULP composite clock during initialization
   - Add CLK_SET_RATE_NO_REPARENT flag to the i.MX7ULP composite
   - Disable the i.MX pfd when set pfdv2 clock rate
   - Add support for i.MX8ULP in pfdv2
   - Add the pcc reset controller support on i.MX8ULP
   - Fix the build break when clk-imx8ulp is built as module
   - Move csi_sel mux to correct base register in i.MX6UL clock drivr
   - Fix csi clk gate register in i.MX6UL clock driver
   - Fix build bug making CLK_IMX8ULP select MXC_CLK
   - Add TPU (PWM), and Z (Cortex-A76) clocks on Renesas R-Car V3U
   - Add Ethernet clocks on Renesas RZ/G2L
   - Move Rockchip to use module_platform_probe
   - Enable usage of Coresight related clocks on Rockchip rk3399"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (170 commits)
  clk: use clk_core_get_rate_recalc() in clk_rate_get()
  clk: at91: sama7g5: set low limit for mck0 at 32KHz
  clk: at91: sama7g5: remove prescaler part of master clock
  clk: at91: clk-master: add notifier for divider
  clk: at91: clk-sam9x60-pll: add notifier for div part of PLL
  clk: at91: clk-master: fix prescaler logic
  clk: at91: clk-master: mask mckr against layout->mask
  clk: at91: clk-master: check if div or pres is zero
  clk: at91: sam9x60-pll: use DIV_ROUND_CLOSEST_ULL
  clk: at91: pmc: add sama7g5 to the list of available pmcs
  clk: at91: clk-master: improve readability by using local variables
  clk: at91: clk-master: add register definition for sama7g5's master clock
  clk: at91: sama7g5: add securam's peripheral clock
  clk: at91: pmc: execute suspend/resume only for backup mode
  clk: at91: re-factor clocks suspend/resume
  clk: ux500: Add driver for the reset portions of PRCC
  dt-bindings: clock: u8500: Rewrite in YAML and extend
  clk: composite: Use rate_ops.determine_rate when also a mux is available
  clk: samsung: describe drivers in Kconfig
  clk: samsung: exynos5433: update apollo and atlas clock probing
  ...
clk: qcom: smd-rpm: Add QCM2290 RPM clock support 2021-10-13T22:20:22+00:00 Shawn Guo shawn.guo@linaro.org 2021-09-17T03:04:34+00:00 78b727d0281507fabf954573420790b21e34aefe Add support for RPM-managed clocks on the QCM2290 platform. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Link: https://lore.kernel.org/r/20210917030434.19859-4-shawn.guo@linaro.org Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> 
Add support for RPM-managed clocks on the QCM2290 platform.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Link: https://lore.kernel.org/r/20210917030434.19859-4-shawn.guo@linaro.org
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Merge tag '20210927135559.738-6-srinivas.kandagatla@linaro.org' into drivers-for-5.16 2021-09-28T03:13:45+00:00 Bjorn Andersson bjorn.andersson@linaro.org 2021-09-28T03:13:45+00:00 f27591125a56c8c50491919b159569ab5730878d v5.15-rc1 + 20210927135559.738-[23456]-srinivas.kandagatla@linaro.org This immutable branch is based on v5.15-rc1 and contains the following patches extending the existig APR driver to also implement GPR: 20210927135559.738-2-srinivas.kandagatla@linaro.org 20210927135559.738-3-srinivas.kandagatla@linaro.org 20210927135559.738-4-srinivas.kandagatla@linaro.org 20210927135559.738-5-srinivas.kandagatla@linaro.org 20210927135559.738-6-srinivas.kandagatla@linaro.org 
v5.15-rc1 + 20210927135559.738-[23456]-srinivas.kandagatla@linaro.org

This immutable branch is based on v5.15-rc1 and contains the following
patches extending the existig APR driver to also implement GPR:
20210927135559.738-2-srinivas.kandagatla@linaro.org
20210927135559.738-3-srinivas.kandagatla@linaro.org
20210927135559.738-4-srinivas.kandagatla@linaro.org
20210927135559.738-5-srinivas.kandagatla@linaro.org
20210927135559.738-6-srinivas.kandagatla@linaro.org
soc: qcom: apr: Add GPR support 2021-09-28T03:10:07+00:00 Srinivas Kandagatla srinivas.kandagatla@linaro.org 2021-09-27T13:55:42+00:00 ec1471a898cca38af6b8956a83ebc1297214546f Qualcomm Generic Packet router aka GPR is the IPC mechanism found in AudioReach next generation signal processing framework to perform command and response messages between various processors. GPR has concepts of static and dynamic port, all static services like APM (Audio Processing Manager), PRM (Proxy resource manager) have fixed port numbers where as dynamic services like graphs have dynamic port numbers which are allocated at runtime. All GPR packet messages will have source and destination domain and port along with opcode and payload. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210927135559.738-6-srinivas.kandagatla@linaro.org 
Qualcomm Generic Packet router aka GPR is the IPC mechanism found
in AudioReach next generation signal processing framework to perform
command and response messages between various processors.

GPR has concepts of static and dynamic port, all static services like
APM (Audio Processing Manager), PRM (Proxy resource manager) have
fixed port numbers where as dynamic services like graphs have dynamic
port numbers which are allocated at runtime. All GPR packet messages
will have source and destination domain and port along with opcode
and payload.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210927135559.738-6-srinivas.kandagatla@linaro.org
soc: qcom: apr: make code more reuseable 2021-09-28T03:10:07+00:00 Srinivas Kandagatla srinivas.kandagatla@linaro.org 2021-09-27T13:55:40+00:00 99139b80c1b3d73026ed8be2de42c52e2976ab64 APR and other packet routers like GPR are pretty much same and interact with other drivers in similar way. Ex: GPR ports can be considered as APR services, only difference is they are allocated dynamically. Other difference is packet layout, which should not matter with the apis abstracted. Apart from this the rest of the functionality is pretty much identical across APR and GPR. Make the apr code more reusable by abstracting it service level, rather than device level so that we do not need to write new drivers for other new packet routers like GPR. This patch is in preparation to add GPR support to this driver. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210927135559.738-4-srinivas.kandagatla@linaro.org 
APR and other packet routers like GPR are pretty much same and
interact with other drivers in similar way.

Ex: GPR ports can be considered as APR services, only difference
is they are allocated dynamically.

Other difference is packet layout, which should not matter
with the apis abstracted. Apart from this the rest of the
functionality is pretty much identical across APR and GPR.

Make the apr code more reusable by abstracting it service level,
rather than device level so that we do not need to write
new drivers for other new packet routers like GPR.

This patch is in preparation to add GPR support to this driver.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210927135559.738-4-srinivas.kandagatla@linaro.org
soc: qcom: aoss: Expose send for generic usecase 2021-09-21T22:31:18+00:00 Deepak Kumar Singh deesin@codeaurora.org 2021-08-31T14:30:27+00:00 8c75d585b931ac874fbe4ee5a8f1811d20c2817f Not all upcoming usecases will have an interface to allow the aoss driver to hook onto. Expose the send api and create a get function to enable drivers to send their own messages to aoss. Signed-off-by: Chris Lew <clew@codeaurora.org> Signed-off-by: Deepak Kumar Singh <deesin@codeaurora.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1630420228-31075-2-git-send-email-deesin@codeaurora.org 
Not all upcoming usecases will have an interface to allow the aoss
driver to hook onto. Expose the send api and create a get function to
enable drivers to send their own messages to aoss.

Signed-off-by: Chris Lew <clew@codeaurora.org>
Signed-off-by: Deepak Kumar Singh <deesin@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1630420228-31075-2-git-send-email-deesin@codeaurora.org
clk: qcom: smd: Add support for SM6125 rpm clocks 2021-08-06T01:27:56+00:00 Martin Botka martin.botka@somainline.org 2021-07-30T21:59:24+00:00 edeb2ca74716056b2be62925f21494d7af65150f Add rpm smd clocks, PMIC and bus clocks which are required on SM6125 for clients to vote on. Signed-off-by: Martin Botka <martin.botka@somainline.org> Link: https://lore.kernel.org/r/20210730215924.733350-2-martin.botka@somainline.org Signed-off-by: Stephen Boyd <sboyd@kernel.org> 
Add rpm smd clocks, PMIC and bus clocks which are required on SM6125
for clients to vote on.

Signed-off-by: Martin Botka <martin.botka@somainline.org>
Link: https://lore.kernel.org/r/20210730215924.733350-2-martin.botka@somainline.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
soc: qcom: smem_state: Add devm_qcom_smem_state_get() 2021-06-23T18:35:12+00:00 Stephan Gerhold stephan@gerhold.net 2021-06-18T11:15:54+00:00 61d1961adf4bd57d1b2c6d94d97323263c470cb2 It is easy to forget to call qcom_smem_state_put() after a qcom_smem_state_get(). Introduce a devm_qcom_smem_state_get() helper function that automates this so that qcom_smem_state_put() is automatically called when a device is removed. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210618111556.53416-1-stephan@gerhold.net Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> 
It is easy to forget to call qcom_smem_state_put() after
a qcom_smem_state_get(). Introduce a devm_qcom_smem_state_get()
helper function that automates this so that qcom_smem_state_put()
is automatically called when a device is removed.

Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210618111556.53416-1-stephan@gerhold.net
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
soc: qcom: address kernel-doc warnings 2021-03-30T03:49:54+00:00 Lukas Bulwahn lukas.bulwahn@gmail.com 2021-03-27T06:56:42+00:00 8058dfa05ab765153f20020fc4ea3b296e391a00 The command: find ./include/linux/soc/qcom/ | xargs ./scripts/kernel-doc -none reports: ./include/linux/soc/qcom/qmi.h:26: warning: cannot understand function prototype: 'struct qmi_header ' ./include/linux/soc/qcom/qmi.h:101: warning: cannot understand function prototype: 'struct qmi_response_type_v01 ' ./include/linux/soc/qcom/irq.h:19: warning: expecting prototype for QCOM specific IRQ domain flags that distinguishes the handling of wakeup(). Prototype was for IRQ_DOMAIN_FLAG_QCOM_PDC_WAKEUP() instead ./include/linux/soc/qcom/apr.h:126: warning: Function parameter or member '__apr_driver' not described in 'module_apr_driver' ./include/linux/soc/qcom/apr.h:126: warning: Excess function parameter '__aprbus_driver' description in 'module_apr_driver' ./include/linux/soc/qcom/llcc-qcom.h:43: warning: cannot understand function prototype: 'struct llcc_slice_desc ' ./include/linux/soc/qcom/llcc-qcom.h:60: warning: cannot understand function prototype: 'struct llcc_edac_reg_data ' ./include/linux/soc/qcom/llcc-qcom.h:86: warning: cannot understand function prototype: 'struct llcc_drv_data ' Address all those warnings by: - prefixing kernel-doc descriptions for structs with the keyword 'struct', - turning a kernel-doc comment that does not follow the kernel-doc syntax into a normal comment, and - correcting a parameter name in a kernel-doc comment. Signed-off-by: Lukas Bulwahn <lukas.bulwahn@gmail.com> Link: https://lore.kernel.org/r/20210327065642.11969-3-lukas.bulwahn@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> 
The command:

  find ./include/linux/soc/qcom/ | xargs ./scripts/kernel-doc -none

reports:

  ./include/linux/soc/qcom/qmi.h:26: warning: cannot understand function prototype: 'struct qmi_header '
  ./include/linux/soc/qcom/qmi.h:101: warning: cannot understand function prototype: 'struct qmi_response_type_v01 '
  ./include/linux/soc/qcom/irq.h:19: warning: expecting prototype for QCOM specific IRQ domain flags that distinguishes the handling of wakeup(). Prototype was for IRQ_DOMAIN_FLAG_QCOM_PDC_WAKEUP() instead
  ./include/linux/soc/qcom/apr.h:126: warning: Function parameter or member '__apr_driver' not described in 'module_apr_driver'
  ./include/linux/soc/qcom/apr.h:126: warning: Excess function parameter '__aprbus_driver' description in 'module_apr_driver'
  ./include/linux/soc/qcom/llcc-qcom.h:43: warning: cannot understand function prototype: 'struct llcc_slice_desc '
  ./include/linux/soc/qcom/llcc-qcom.h:60: warning: cannot understand function prototype: 'struct llcc_edac_reg_data '
  ./include/linux/soc/qcom/llcc-qcom.h:86: warning: cannot understand function prototype: 'struct llcc_drv_data '

Address all those warnings by:
  - prefixing kernel-doc descriptions for structs with the keyword 'struct',
  - turning a kernel-doc comment that does not follow the kernel-doc syntax
  into a normal comment, and
  - correcting a parameter name in a kernel-doc comment.

Signed-off-by: Lukas Bulwahn <lukas.bulwahn@gmail.com>
Link: https://lore.kernel.org/r/20210327065642.11969-3-lukas.bulwahn@gmail.com
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>