linux-toradex.git/include/soc/at91, branch v4.4.93 Linux kernel for Apalis and Colibri modules ARM: at91: define LPDDR types 2017-03-12T05:37:24+00:00 Alexandre Belloni alexandre.belloni@free-electrons.com 2016-10-25T09:37:58+00:00 b401418c6cc3c7eeb3376d4ca57334680d1df8d9 commit e3f0a4017c2143b4b813df6a93e8cf79e3f76936 upstream. The Atmel MPDDR controller support LPDDR2 and LPDDR3 memories, add their types. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Sebastian Reichel <sre@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> 
commit e3f0a4017c2143b4b813df6a93e8cf79e3f76936 upstream.

The Atmel MPDDR controller support LPDDR2 and LPDDR3 memories, add their
types.

Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Sebastian Reichel <sre@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
ARM: at91: remove at91rm9200_sdramc.h 2015-05-20T14:37:55+00:00 Alexandre Belloni alexandre.belloni@free-electrons.com 2015-03-16T14:25:01+00:00 a11683b72da7552b724ee21760df5d19cf53f031 include/soc/at91/at91rm9200_sdramc.h is replaced by include/linux/mfd/syscon/atmel-smc.h as this is actually a syscon device. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> 
include/soc/at91/at91rm9200_sdramc.h is replaced by
include/linux/mfd/syscon/atmel-smc.h as this is actually a syscon device.

Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
pm: at91: Workaround DDRSDRC self-refresh bug with LPDDR1 memories. 2015-03-03T18:43:59+00:00 Peter Rosin peda@axentia.se 2015-02-05T06:02:09+00:00 02f513a0970d97e4fc5f262f5a6c814014af524e The DDRSDR controller fails miserably to put LPDDR1 memories in self-refresh. Force the controller to think it has DDR2 memories during the self-refresh period, as the DDR2 self-refresh spec is equivalent to LPDDR1, and is correctly implemented in the controller. Assume that the second controller has the same fault, but that is untested. Signed-off-by: Peter Rosin <peda@axentia.se> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> 
The DDRSDR controller fails miserably to put LPDDR1 memories in
self-refresh. Force the controller to think it has DDR2 memories
during the self-refresh period, as the DDR2 self-refresh spec is
equivalent to LPDDR1, and is correctly implemented in the
controller.

Assume that the second controller has the same fault, but that is
untested.

Signed-off-by: Peter Rosin <peda@axentia.se>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
ARM: at91: move sdramc/ddrsdr header to include/soc/at91 2014-11-13T11:03:44+00:00 Alexandre Belloni alexandre.belloni@free-electrons.com 2014-11-07T20:58:21+00:00 f0a0a58e6f46c2dded813ee860b9cbd795b4e571 Move the (DDR) SDRAM controller headers to include/soc/at91 to remove the dependency on mach/ headers from the at91-reset driver. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> 
Move the (DDR) SDRAM controller headers to include/soc/at91 to remove the
dependency on mach/ headers from the at91-reset driver.

Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>