linux-toradex.git/include/soc/microchip, branch v6.8-rc7 Linux kernel for Apalis and Colibri modules soc: microchip: mpfs: enable access to the system controller's flash 2023-12-06T12:06:18+00:00 Conor Dooley conor.dooley@microchip.com 2023-10-20T13:18:40+00:00 742aa6c563d29c367edbf0ef7236a7a853ed9be4 The system controller has a flash that contains images used to reprogram the FPGA using IAP (In-Application Programming). Introduce a function that allows a driver with a reference to the system controller to get one to a flash device attached to it. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> 
The system controller has a flash that contains images used to reprogram
the FPGA using IAP (In-Application Programming).
Introduce a function that allows a driver with a reference to the system
controller to get one to a flash device attached to it.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
clk: microchip: mpfs: add reset controller 2022-09-14T07:55:17+00:00 Conor Dooley conor.dooley@microchip.com 2022-09-09T12:31:13+00:00 b56bae2dd6fda6baf3bb74af3812676eebdd52f2 Add a reset controller to PolarFire SoC's clock driver. This reset controller is registered as an aux device and read/write functions exported to the drivers namespace so that the reset controller can access the peripheral device reset register. Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220909123123.2699583-5-conor.dooley@microchip.com 
Add a reset controller to PolarFire SoC's clock driver. This reset
controller is registered as an aux device and read/write functions
exported to the drivers namespace so that the reset controller can
access the peripheral device reset register.

Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220909123123.2699583-5-conor.dooley@microchip.com
soc: add microchip polarfire soc system controller 2022-02-25T11:50:59+00:00 Conor Dooley conor.dooley@microchip.com 2022-02-17T10:13:50+00:00 d0054a470c33902f5ae88835ed8a8ecc3cf8faa4 This driver provides an interface for other drivers to access the functions of the system controller on the Microchip PolarFire SoC. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20220217101349.2374873-2-conor.dooley@microchip.com 
This driver provides an interface for other drivers to access the
functions of the system controller on the Microchip PolarFire SoC.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/r/20220217101349.2374873-2-conor.dooley@microchip.com
mbox: add polarfire soc system controller mailbox 2021-06-26T17:06:48+00:00 Conor Dooley conor.dooley@microchip.com 2021-06-24T15:00:55+00:00 83d7b1560810e038e1d07ca6bff41edaeae29725 This driver adds support for the single mailbox channel of the MSS system controller on the Microchip PolarFire SoC. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org> 
This driver adds support for the single mailbox channel of the MSS
system controller on the Microchip PolarFire SoC.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>