linux-toradex.git/include/soc/qcom, branch v6.0-rc1 Linux kernel for Apalis and Colibri modules mfd: qcom-spmi-pmic: read fab id on supported PMICs 2022-06-18T13:01:16+00:00 Caleb Connolly caleb.connolly@linaro.org 2022-04-29T22:08:58+00:00 d23c3c085a95fddae5143823b7d5a81419e6f497 The PMI8998 and PM660 expose the fab_id, this is needed by drivers like the RRADC to calibrate ADC values. Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Acked-by: Lee Jones <lee.jones@linaro.org> Link: https://lore.kernel.org/r/20220429220904.137297-4-caleb.connolly@linaro.org Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> 
The PMI8998 and PM660 expose the fab_id, this is needed by drivers like
the RRADC to calibrate ADC values.

Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Acked-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20220429220904.137297-4-caleb.connolly@linaro.org
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
mfd: qcom-spmi-pmic: expose the PMIC revid information to clients 2022-06-18T13:01:16+00:00 Caleb Connolly caleb.connolly@linaro.org 2022-04-29T22:08:57+00:00 e9c11c6e3a0e93903f5a13f8d2f97ae1bba512e1 Some PMIC functions such as the RRADC need to be aware of the PMIC chip revision information to implement errata or otherwise adjust behaviour, export the PMIC information to enable this. This is specifically required to enable the RRADC to adjust coefficients based on which chip fab the PMIC was produced in, this can vary per unique device and therefore has to be read at runtime. Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Acked-by: Lee Jones <lee.jones@linaro.org> Link: https://lore.kernel.org/r/20220429220904.137297-3-caleb.connolly@linaro.org Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> 
Some PMIC functions such as the RRADC need to be aware of the PMIC
chip revision information to implement errata or otherwise adjust
behaviour, export the PMIC information to enable this.

This is specifically required to enable the RRADC to adjust
coefficients based on which chip fab the PMIC was produced in,
this can vary per unique device and therefore has to be read at
runtime.

Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Acked-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20220429220904.137297-3-caleb.connolly@linaro.org
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
soc: qcom: spm: Implement support for SAWv4.1, SDM630/660 L2 AVS 2021-09-21T22:41:48+00:00 AngeloGioacchino Del Regno angelogioacchino.delregno@somainline.org 2021-07-29T15:56:07+00:00 13e72c3e22611915f9a71a513b640e064a403e78 Implement the support for SAW v4.1, used in at least MSM8998, SDM630, SDM660 and APQ variants and, while at it, also add the configuration for the SDM630/660 Silver and Gold cluster L2 Adaptive Voltage Scaler: this is also one of the prerequisites to allow the OSM controller to perform DCVS. Please note that despite there are various "versions" of these values downstream, these are the only ones that are perfectly stable on the entire set of tested devices. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Reviewed-by: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210729155609.608159-4-angelogioacchino.delregno@somainline.org 
Implement the support for SAW v4.1, used in at least MSM8998,
SDM630, SDM660 and APQ variants and, while at it, also add the
configuration for the SDM630/660 Silver and Gold cluster L2
Adaptive Voltage Scaler: this is also one of the prerequisites
to allow the OSM controller to perform DCVS.

Please note that despite there are various "versions" of these
values downstream, these are the only ones that are perfectly
stable on the entire set of tested devices.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Reviewed-by: Stephan Gerhold <stephan@gerhold.net>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210729155609.608159-4-angelogioacchino.delregno@somainline.org
cpuidle: qcom_spm: Detach state machine from main SPM handling 2021-09-21T22:41:48+00:00 AngeloGioacchino Del Regno angelogioacchino.delregno@somainline.org 2021-07-29T15:56:05+00:00 60f3692b5f0b3e1df3ccc07c28758379052d0ab6 In commit a871be6b8eee ("cpuidle: Convert Qualcomm SPM driver to a generic CPUidle driver") the SPM driver has been converted to a generic CPUidle driver: that was mainly made to simplify the driver and that was a great accomplishment; Though, at that time, this driver was only applicable to ARM 32-bit SoCs, lacking logic about the handling of newer generation SAW. In preparation for the enablement of SPM features on AArch64/ARM64, split the cpuidle-qcom-spm driver in two: the CPUIdle related state machine (currently used only on ARM SoCs) stays there, while the SPM communication handling lands back in soc/qcom/spm.c and also making sure to not discard the simplifications that were introduced in the aforementioned commit. Since now the "two drivers" are split, the SCM dependency in the main SPM handling is gone and for this reason it was also possible to move the SPM initialization early: this will also make sure that whenever the SAW CPUIdle driver is getting initialized, the SPM driver will be ready to do the job. Please note that the anticipation of the SPM initialization was also done to optimize the boot times on platforms that have their CPU/L2 idle states managed by other means (such as PSCI), while needing SAW initialization for other purposes, like AVS control. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Reviewed-by: Stephan Gerhold <stephan@gerhold.net> Tested-by: Stephan Gerhold <stephan@gerhold.net> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210729155609.608159-2-angelogioacchino.delregno@somainline.org 
In commit a871be6b8eee ("cpuidle: Convert Qualcomm SPM driver to a generic
CPUidle driver") the SPM driver has been converted to a
generic CPUidle driver: that was mainly made to simplify the
driver and that was a great accomplishment;
Though, at that time, this driver was only applicable to ARM 32-bit SoCs,
lacking logic about the handling of newer generation SAW.

In preparation for the enablement of SPM features on AArch64/ARM64,
split the cpuidle-qcom-spm driver in two: the CPUIdle related
state machine (currently used only on ARM SoCs) stays there, while
the SPM communication handling lands back in soc/qcom/spm.c and
also making sure to not discard the simplifications that were
introduced in the aforementioned commit.

Since now the "two drivers" are split, the SCM dependency in the
main SPM handling is gone and for this reason it was also possible
to move the SPM initialization early: this will also make sure that
whenever the SAW CPUIdle driver is getting initialized, the SPM
driver will be ready to do the job.

Please note that the anticipation of the SPM initialization was
also done to optimize the boot times on platforms that have their
CPU/L2 idle states managed by other means (such as PSCI), while
needing SAW initialization for other purposes, like AVS control.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Reviewed-by: Stephan Gerhold <stephan@gerhold.net>
Tested-by: Stephan Gerhold <stephan@gerhold.net>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210729155609.608159-2-angelogioacchino.delregno@somainline.org
soc: qcom: rpmh: Remove serialization of TCS commands 2021-01-07T16:59:46+00:00 Lina Iyer ilina@codeaurora.org 2021-01-07T08:39:30+00:00 fef419c463d0dd95488a9750dc501ae43825e5d2 Requests sent to RPMH can be sent as fire-n-forget or response required, with the latter ensuring the command has been completed by the hardware accelerator. Commands in a request with tcs_cmd::wait set, would ensure that those select commands are sent as response required, even though the actual TCS request may be fire-n-forget. Also, commands with .wait flag were also guaranteed to be complete before the following command in the TCS is sent. This means that the next command of the same request blocked until the current request is completed. This could mean waiting for a voltage to settle or series of NOCs be configured before the next command is sent. But drivers using this feature have never cared about the serialization aspect. By not enforcing the serialization we can allow the hardware to run in parallel improving the performance. Let's clarify the usage of this member in the tcs_cmd structure to mean only completion and not serialization. This should also improve the performance of bus requests where changes could happen in parallel. Also, CPU resume from deep idle may see benefits from certain wake requests. Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Lina Iyer <ilina@codeaurora.org> Signed-off-by: Maulik Shah <mkshah@codeaurora.org> Link: https://lore.kernel.org/r/1610008770-13891-1-git-send-email-mkshah@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> 
Requests sent to RPMH can be sent as fire-n-forget or response required,
with the latter ensuring the command has been completed by the hardware
accelerator. Commands in a request with tcs_cmd::wait set, would ensure
that those select commands are sent as response required, even though
the actual TCS request may be fire-n-forget.

Also, commands with .wait flag were also guaranteed to be complete
before the following command in the TCS is sent. This means that the
next command of the same request blocked until the current request is
completed. This could mean waiting for a voltage to settle or series of
NOCs be configured before the next command is sent. But drivers using
this feature have never cared about the serialization aspect. By not
enforcing the serialization we can allow the hardware to run in parallel
improving the performance.

Let's clarify the usage of this member in the tcs_cmd structure to mean
only completion and not serialization. This should also improve the
performance of bus requests where changes could happen in parallel.
Also, CPU resume from deep idle may see benefits from certain wake
requests.

Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Lina Iyer <ilina@codeaurora.org>
Signed-off-by: Maulik Shah <mkshah@codeaurora.org>
Link: https://lore.kernel.org/r/1610008770-13891-1-git-send-email-mkshah@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux 2020-08-07T20:35:51+00:00 Linus Torvalds torvalds@linux-foundation.org 2020-08-07T20:35:51+00:00 30185b69a2d533c4ba6ca926b8390ce7de495e29 Pull clk updates from Stephen Boyd: "It looks like a smaller batch of clk updates this time around. In the core framework we just have some minor tweaks and a debugfs feature, so not much to see there. The driver updates are fairly well split between AT91 and Qualcomm clk support. Adding those two drivers together equals about 50% of the diffstat. Otherwise, the big amount of work this time was on supporting Broadcom's Raspberry Pi firmware clks. Highlights: Core: - Document clk_hw_round_rate() so it gets some more use - Remove unused __clk_get_flags() - Add a prepare/enable debugfs feature similar to rate setting New Drivers: - Add support for SAMA7G5 SoC clks - Enable CPU clks on Qualcomm IPQ6018 SoCs - Enable CPU clks on Qualcomm MSM8996 SoCs - GPU clk support for Qualcomm SM8150 and SM8250 SoCs - Audio clks on Qualcomm SC7180 SoCs - Microchip Sparx5 DPLL clk - Add support for the new Renesas RZ/G2H (R8A774E1) SoC Updates: - Make defines for bcm63xx-gate clks to use in DT - Support BCM2711 SoC firmware clks - Add HDMI clks for BCM2711 SoCs - Add RTC related clks on Ingenic SoCs - Support USB PHY clks on Ingenic SoCs - Support gate clks on BCM6318 SoCs - RMU and DMAC/GPIO clock support for Actions Semi S500 SoCs - Use poll_timeout functions in Rockchip clk driver - Support Rockchip rk3288w SoC variant - Mark mac_lbtest critical on Rockchip rk3188 - Add CAAM clock support for i.MX vf610 driver - Add MU root clock support for i.MX imx8mp driver - Amlogic g12: add neural network accelerator clock sources - Amlogic meson8: remove critical flag for main PLL divider - Amlogic meson8: add video decoder clock gates - Convert one more Renesas DT binding to json-schema - Enhance critical clock handling on Renesas platforms to only consider clocks that were enabled at boot time" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (79 commits) clk: qcom: gcc: Make disp gpll0 branch aon for sc7180/sdm845 ipq806x: gcc: add support for child probe clk: qcom: msm8996: Make symbol 'cpu_msm8996_clks' static clk: qcom: ipq8074: Add correct index for PCIe clocks clk: <linux/clk-provider.h>: drop a duplicated word clk: renesas: cpg-mssr: Add r8a774e1 support dt-bindings: clock: renesas,cpg-mssr: Document r8a774e1 clk: Drop duplicate selection in Kconfig clk: qcom: smd: Add support for MSM8992/4 rpm clocks clk: qcom: ipq8074: Add missing clocks for pcie dt-bindings: clock: qcom: ipq8074: Add missing bindings for PCIe Replace HTTP links with HTTPS ones: Common CLK framework clk: qcom: Add CPU clock driver for msm8996 dt-bindings: clk: qcom: Add bindings for CPU clock for msm8996 soc: qcom: Separate kryo l2 accessors from PMU driver clk: meson: meson8b: add the vclk2_en gate clock clk: meson: meson8b: add the vclk_en gate clock clk: qcom: Fix return value check in apss_ipq6018_probe() clk: bcm: dvp: Add missing module informations clk: meson: meson8b: Drop CLK_IS_CRITICAL from fclk_div2 ... 
Pull clk updates from Stephen Boyd:
 "It looks like a smaller batch of clk updates this time around.

  In the core framework we just have some minor tweaks and a debugfs
  feature, so not much to see there. The driver updates are fairly well
  split between AT91 and Qualcomm clk support. Adding those two drivers
  together equals about 50% of the diffstat.

  Otherwise, the big amount of work this time was on supporting
  Broadcom's Raspberry Pi firmware clks.

  Highlights:

  Core:
   - Document clk_hw_round_rate() so it gets some more use
   - Remove unused __clk_get_flags()
   - Add a prepare/enable debugfs feature similar to rate setting

  New Drivers:
   - Add support for SAMA7G5 SoC clks
   - Enable CPU clks on Qualcomm IPQ6018 SoCs
   - Enable CPU clks on Qualcomm MSM8996 SoCs
   - GPU clk support for Qualcomm SM8150 and SM8250 SoCs
   - Audio clks on Qualcomm SC7180 SoCs
   - Microchip Sparx5 DPLL clk
   - Add support for the new Renesas RZ/G2H (R8A774E1) SoC

  Updates:
   - Make defines for bcm63xx-gate clks to use in DT
   - Support BCM2711 SoC firmware clks
   - Add HDMI clks for BCM2711 SoCs
   - Add RTC related clks on Ingenic SoCs
   - Support USB PHY clks on Ingenic SoCs
   - Support gate clks on BCM6318 SoCs
   - RMU and DMAC/GPIO clock support for Actions Semi S500 SoCs
   - Use poll_timeout functions in Rockchip clk driver
   - Support Rockchip rk3288w SoC variant
   - Mark mac_lbtest critical on Rockchip rk3188
   - Add CAAM clock support for i.MX vf610 driver
   - Add MU root clock support for i.MX imx8mp driver
   - Amlogic g12: add neural network accelerator clock sources
   - Amlogic meson8: remove critical flag for main PLL divider
   - Amlogic meson8: add video decoder clock gates
   - Convert one more Renesas DT binding to json-schema
   - Enhance critical clock handling on Renesas platforms to only
     consider clocks that were enabled at boot time"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (79 commits)
  clk: qcom: gcc: Make disp gpll0 branch aon for sc7180/sdm845
  ipq806x: gcc: add support for child probe
  clk: qcom: msm8996: Make symbol 'cpu_msm8996_clks' static
  clk: qcom: ipq8074: Add correct index for PCIe clocks
  clk: <linux/clk-provider.h>: drop a duplicated word
  clk: renesas: cpg-mssr: Add r8a774e1 support
  dt-bindings: clock: renesas,cpg-mssr: Document r8a774e1
  clk: Drop duplicate selection in Kconfig
  clk: qcom: smd: Add support for MSM8992/4 rpm clocks
  clk: qcom: ipq8074: Add missing clocks for pcie
  dt-bindings: clock: qcom: ipq8074: Add missing bindings for PCIe
  Replace HTTP links with HTTPS ones: Common CLK framework
  clk: qcom: Add CPU clock driver for msm8996
  dt-bindings: clk: qcom: Add bindings for CPU clock for msm8996
  soc: qcom: Separate kryo l2 accessors from PMU driver
  clk: meson: meson8b: add the vclk2_en gate clock
  clk: meson: meson8b: add the vclk_en gate clock
  clk: qcom: Fix return value check in apss_ipq6018_probe()
  clk: bcm: dvp: Add missing module informations
  clk: meson: meson8b: Drop CLK_IS_CRITICAL from fclk_div2
  ...
soc: qcom: Separate kryo l2 accessors from PMU driver 2020-07-11T00:08:55+00:00 Ilia Lin ilialin@codeaurora.org 2020-07-03T08:49:41+00:00 6d0efeb14bbe2350a94ba07b403a686d731c5179 The driver provides kernel level API for other drivers to access the MSM8996 L2 cache registers. Separating the L2 access code from the PMU driver and making it public to allow other drivers use it. The accesses must be separated with a single spinlock, maintained in this driver. Signed-off-by: Ilia Lin <ilialin@codeaurora.org> Signed-off-by: Loic Poulain <loic.poulain@linaro.org> Link: https://lore.kernel.org/r/1593766185-16346-2-git-send-email-loic.poulain@linaro.org Acked-by: Will Deacon <will@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> 
The driver provides kernel level API for other drivers
to access the MSM8996 L2 cache registers.
Separating the L2 access code from the PMU driver and
making it public to allow other drivers use it.
The accesses must be separated with a single spinlock,
maintained in this driver.

Signed-off-by: Ilia Lin <ilialin@codeaurora.org>
Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
Link: https://lore.kernel.org/r/1593766185-16346-2-git-send-email-loic.poulain@linaro.org
Acked-by: Will Deacon <will@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
soc: qcom: rpmh: Update rpmh_invalidate function to return void 2020-06-22T21:23:46+00:00 Maulik Shah mkshah@codeaurora.org 2020-06-18T13:05:53+00:00 73edcd38d7720bb6a761966ea14c0bc64e95dc26 Currently rpmh_invalidate() always returns success. Update its return type to void. Reviewed-by: Lina Iyer <ilina@codeaurora.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Suggested-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Maulik Shah <mkshah@codeaurora.org> Link: https://lore.kernel.org/r/1592485553-29163-1-git-send-email-mkshah@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> 
Currently rpmh_invalidate() always returns success. Update its
return type to void.

Reviewed-by: Lina Iyer <ilina@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Suggested-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Maulik Shah <mkshah@codeaurora.org>
Link: https://lore.kernel.org/r/1592485553-29163-1-git-send-email-mkshah@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
soc: qcom: cmd-db: Fix compilation error when CMD_DB is disabled 2020-04-14T01:10:10+00:00 Sibi Sankar sibis@codeaurora.org 2020-02-27T12:56:15+00:00 7ad18bb5c2c4bd50c8b83d375ee19be992022cf3 If CONFIG_QCOM_COMMAND_DB=n the following compilation errors will be seen. Fix this by including the appropriate linux headers. ./include/soc/qcom/cmd-db.h: In function ‘cmd_db_read_aux_data’: ./include/soc/qcom/cmd-db.h: error: implicit declaration of function ‘ERR_PTR’; Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Link: https://lore.kernel.org/r/20200227125615.4727-1-sibis@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> 
If CONFIG_QCOM_COMMAND_DB=n the following compilation errors will be
seen. Fix this by including the appropriate linux headers.

./include/soc/qcom/cmd-db.h: In function ‘cmd_db_read_aux_data’:
./include/soc/qcom/cmd-db.h: error: implicit declaration of function ‘ERR_PTR’;

Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Link: https://lore.kernel.org/r/20200227125615.4727-1-sibis@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
drivers: qcom: rpmh: remove rpmh_flush export 2020-02-12T06:15:02+00:00 Maulik Shah mkshah@codeaurora.org 2020-02-03T13:35:35+00:00 d5e205079c34aa1f33157627814f707d6057727a rpmh_flush() was exported with the idea that an external entity operation during CPU idle would know when to flush the sleep and wake TCS. Since, this is not the case when defining a power domain for the RSC. Remove the function export and instead allow the function to be called internally. Signed-off-by: Maulik Shah <mkshah@codeaurora.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/1580736940-6985-3-git-send-email-mkshah@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> 
rpmh_flush() was exported with the idea that an external entity
operation during CPU idle would know when to flush the sleep and wake
TCS. Since, this is not the case when defining a power domain for the
RSC. Remove the function export and instead allow the function to be
called internally.

Signed-off-by: Maulik Shah <mkshah@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/1580736940-6985-3-git-send-email-mkshah@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>