linux-toradex.git/include/uapi/drm, branch v6.19-rc2

drm/xe: Limit num_syncs to prevent oversized allocations

2025-12-18T17:10:34+00:00

The exec and vm_bind ioctl allow userspace to specify an arbitrary
num_syncs value. Without bounds checking, a very large num_syncs
can force an excessively large allocation, leading to kernel warnings
from the page allocator as below.

Introduce DRM_XE_MAX_SYNCS (set to 1024) and reject any request
exceeding this limit.

"
------------[ cut here ]------------
WARNING: CPU: 0 PID: 1217 at mm/page_alloc.c:5124 __alloc_frozen_pages_noprof+0x2f8/0x2180 mm/page_alloc.c:5124
...
Call Trace:
 
 alloc_pages_mpol+0xe4/0x330 mm/mempolicy.c:2416
 ___kmalloc_large_node+0xd8/0x110 mm/slub.c:4317
 __kmalloc_large_node_noprof+0x18/0xe0 mm/slub.c:4348
 __do_kmalloc_node mm/slub.c:4364 [inline]
 __kmalloc_noprof+0x3d4/0x4b0 mm/slub.c:4388
 kmalloc_noprof include/linux/slab.h:909 [inline]
 kmalloc_array_noprof include/linux/slab.h:948 [inline]
 xe_exec_ioctl+0xa47/0x1e70 drivers/gpu/drm/xe/xe_exec.c:158
 drm_ioctl_kernel+0x1f1/0x3e0 drivers/gpu/drm/drm_ioctl.c:797
 drm_ioctl+0x5e7/0xc50 drivers/gpu/drm/drm_ioctl.c:894
 xe_drm_ioctl+0x10b/0x170 drivers/gpu/drm/xe/xe_device.c:224
 vfs_ioctl fs/ioctl.c:51 [inline]
 __do_sys_ioctl fs/ioctl.c:598 [inline]
 __se_sys_ioctl fs/ioctl.c:584 [inline]
 __x64_sys_ioctl+0x18b/0x210 fs/ioctl.c:584
 do_syscall_x64 arch/x86/entry/syscall_64.c:63 [inline]
 do_syscall_64+0xbb/0x380 arch/x86/entry/syscall_64.c:94
 entry_SYSCALL_64_after_hwframe+0x77/0x7f
...
"

v2: Add "Reported-by" and Cc stable kernels.
v3: Change XE_MAX_SYNCS from 64 to 1024. (Matt & Ashutosh)
v4: s/XE_MAX_SYNCS/DRM_XE_MAX_SYNCS/ (Matt)
v5: Do the check at the top of the exec func. (Matt)

Fixes: dd08ebf6c352 ("drm/xe: Introduce a new DRM driver for Intel GPUs")
Reported-by: Koen Koning 
Reported-by: Peter Senna Tschudin 
Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/6450
Cc:  # v6.12+
Cc: Matthew Brost 
Cc: Michal Mrozek 
Cc: Carl Zhang 
Cc: José Roberto de Souza 
Cc: Lionel Landwerlin 
Cc: Ivan Briano 
Cc: Thomas Hellström 
Cc: Ashutosh Dixit 
Signed-off-by: Shuicheng Lin 
Reviewed-by: Matthew Brost 
Signed-off-by: Matthew Brost 
Link: https://patch.msgid.link/20251205234715.2476561-5-shuicheng.lin@intel.com
(cherry picked from commit b07bac9bd708ec468cd1b8a5fe70ae2ac9b0a11c)
Signed-off-by: Thomas Hellström

Merge tag 'drm-misc-next-2025-12-01-1' of https://gitlab.freedesktop.org/drm/misc/kernel into drm-next

2025-12-02T08:09:08+00:00

Extra drm-misc-next for v6.19-rc1:

UAPI Changes:
- Add support for drm colorop pipeline.
- Add COLOR PIPELINE plane property.
- Add DRM_CLIENT_CAP_PLANE_COLOR_PIPELINE.

Cross-subsystem Changes:
- Attempt to use higher order mappings in system heap allocator.
- Always taint kernel with sw-sync.

Core Changes:
- Small fixes to drm/gem.
- Support emergency restore to drm-client.
- Allocate and release fb_info in single place.
- Rework ttm pipelined eviction fence handling.

Driver Changes:
- Support the drm color pipeline in vkms, amdgfx.
- Add NVJPG driver for tegra.
- Assorted small fixes and updates to rockchip, bridge/dw-hdmi-qp,
  panthor.
- Add ASL CS5263 DP-to-HDMI simple bridge.
- Add and improve support for G LD070WX3-SL01 MIPI DSI, Samsung LTL106AL0,
  Samsung LTL106AL01, Raystar RFF500F-AWH-DNN, Winstar WF70A8SYJHLNGA,
  Wanchanglong w552946aaa, Samsung SOFEF00, Lenovo X13s panel.
- Add support for it66122 to it66121.
- Support mali-G1 gpu in panthor.

Signed-off-by: Dave Airlie 

From: Maarten Lankhorst 
Link: https://patch.msgid.link/aa5cbd50-7676-4a59-bbed-e8428af86804@linux.intel.com

drm/colorop: Add 3D LUT support to color pipeline

2025-11-26T22:09:42+00:00

It is to be used to enable HDR by allowing userpace to create and pass
3D LUTs to kernel and hardware.

new drm_colorop_type: DRM_COLOROP_3D_LUT.

Reviewed-by: Simon Ser 
Signed-off-by: Alex Hung 
Reviewed-by: Daniel Stone 
Reviewed-by: Melissa Wen 
Reviewed-by: Sebastian Wick 
Signed-off-by: Simon Ser 
Link: https://patch.msgid.link/20251115000237.3561250-46-alex.hung@amd.com

drm/colorop: Define LUT_1D interpolation

2025-11-26T22:09:14+00:00

We want to make sure userspace is aware of the 1D LUT
interpolation. While linear interpolation is common it
might not be supported on all HW. Give driver implementers
a way to specify their interpolation.

Reviewed-by: Simon Ser 
Signed-off-by: Alex Hung 
Signed-off-by: Harry Wentland 
Reviewed-by: Daniel Stone 
Reviewed-by: Melissa Wen 
Reviewed-by: Sebastian Wick 
Signed-off-by: Simon Ser 
Link: https://patch.msgid.link/20251115000237.3561250-44-alex.hung@amd.com

drm/colorop: Add multiplier type

2025-11-26T22:03:35+00:00

This introduces a new drm_colorop_type: DRM_COLOROP_MULTIPLIER.

It's a simple multiplier to all pixel values. The value is
specified via a S31.32 fixed point provided via the
"MULTIPLIER" property.

Reviewed-by: Simon Ser 
Signed-off-by: Alex Hung 
Reviewed-by: Daniel Stone 
Reviewed-by: Melissa Wen 
Reviewed-by: Sebastian Wick 
Signed-off-by: Simon Ser 
Link: https://patch.msgid.link/20251115000237.3561250-41-alex.hung@amd.com

drm/colorop: Add 1D Curve Custom LUT type

2025-11-26T22:03:35+00:00

We've previously introduced DRM_COLOROP_1D_CURVE for
pre-defined 1D curves. But we also have HW that supports
custom curves and userspace needs the ability to pass
custom curves, aka LUTs.

This patch introduces a new colorop type, called
DRM_COLOROP_1D_LUT that provides a SIZE property which
is used by a driver to advertise the supported SIZE
of the LUT, as well as a DATA property which userspace
uses to set the LUT.

DATA and size function in the same way as current drm_crtc
GAMMA and DEGAMMA LUTs.

Reviewed-by: Simon Ser 
Signed-off-by: Alex Hung 
Co-developed-by: Harry Wentland 
Signed-off-by: Harry Wentland 
Reviewed-by: Daniel Stone 
Signed-off-by: Simon Ser 
Link: https://patch.msgid.link/20251115000237.3561250-38-alex.hung@amd.com

drm: Add Enhanced LUT precision structure

2025-11-26T22:03:35+00:00

Existing LUT precision structure drm_color_lut has only 16 bit
precision. This is not enough for upcoming enhanced hardwares
and advance usecases like HDR processing. Hence added a new
structure with 32 bit precision values.

Signed-off-by: Alex Hung 
Signed-off-by: Uma Shankar 
Signed-off-by: Chaitanya Kumar Borah 
Reviewed-by: Sebastian Wick 
Signed-off-by: Simon Ser 
Link: https://patch.msgid.link/20251115000237.3561250-36-alex.hung@amd.com

drm/colorop: Add 3x4 CTM type

2025-11-26T22:03:33+00:00

This type is used to support a 3x4 matrix in colorops. A 3x4
matrix uses the last column as a "bias" column. Some HW exposes
support for 3x4. The calculation looks like:

 out   matrix    in
 |R|   |0  1  2  3 |   | R |
 |G| = |4  5  6  7 | x | G |
 |B|   |8  9  10 11|   | B |
                       |1.0|

This is also the first colorop where we need a blob property to
program the property. For that we'll introduce a new DATA
property that can be used by all colorop TYPEs requiring a
blob. The way a DATA blob is read depends on the TYPE of
the colorop.

We only create the DATA property for property types that
need it.

Reviewed-by: Simon Ser 
Reviewed-by: Louis Chauvet 
Signed-off-by: Alex Hung 
Signed-off-by: Harry Wentland 
Reviewed-by: Daniel Stone 
Reviewed-by: Melissa Wen 
Reviewed-by: Sebastian Wick 
Signed-off-by: Simon Ser 
Link: https://patch.msgid.link/20251115000237.3561250-19-alex.hung@amd.com

drm/colorop: Introduce DRM_CLIENT_CAP_PLANE_COLOR_PIPELINE

2025-11-26T22:03:32+00:00

With the introduction of the pre-blending color pipeline we
can no longer have color operations that don't have a clear
position in the color pipeline. We deprecate all existing
plane properties. For upstream drivers those are:
 - COLOR_ENCODING
 - COLOR_RANGE

Drivers are expected to ignore these properties when
programming the HW. DRM clients that register with
DRM_CLIENT_CAP_PLANE_COLOR_PIPELINE will not be allowed to
set the COLOR_ENCODING and COLOR_RANGE properties.

Setting of the COLOR_PIPELINE plane property or drm_colorop
properties is only allowed for userspace that sets this
client cap.

Reviewed-by: Simon Ser 
Signed-off-by: Alex Hung 
Signed-off-by: Harry Wentland 
Reviewed-by: Daniel Stone 
Reviewed-by: Melissa Wen 
Reviewed-by: Sebastian Wick 
Signed-off-by: Simon Ser 
Link: https://patch.msgid.link/20251115000237.3561250-12-alex.hung@amd.com

drm/colorop: Add TYPE property

2025-11-26T22:03:31+00:00

Add a read-only TYPE property. The TYPE specifies the colorop
type, such as enumerated curve, 1D LUT, CTM, 3D LUT, PWL LUT,
etc.

For now we're only introducing an enumerated 1D LUT type to
illustrate the concept.

Reviewed-by: Simon Ser 
Reviewed-by: Louis Chauvet 
Signed-off-by: Alex Hung 
Signed-off-by: Harry Wentland 
Reviewed-by: Daniel Stone 
Reviewed-by: Melissa Wen 
Reviewed-by: Sebastian Wick 
Signed-off-by: Simon Ser 
Link: https://patch.msgid.link/20251115000237.3561250-6-alex.hung@amd.com