<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux-toradex.git/kernel/irq/msi.c, branch v5.0</title>
<subtitle>Linux kernel for Apalis and Colibri modules</subtitle>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/'/>
<entry>
<title>genirq/core: Introduce struct irq_affinity_desc</title>
<updated>2018-12-19T10:32:08+00:00</updated>
<author>
<name>Dou Liyang</name>
<email>douliyangs@gmail.com</email>
</author>
<published>2018-12-04T15:51:20+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=bec04037e4e484f41ee4d9409e40616874169d20'/>
<id>bec04037e4e484f41ee4d9409e40616874169d20</id>
<content type='text'>
The interrupt affinity management uses straight cpumask pointers to convey
the automatically assigned affinity masks for managed interrupts. The core
interrupt descriptor allocation also decides based on the pointer being non
NULL whether an interrupt is managed or not.

Devices which use managed interrupts usually have two classes of
interrupts:

  - Interrupts for multiple device queues
  - Interrupts for general device management

Currently both classes are treated the same way, i.e. as managed
interrupts. The general interrupts get the default affinity mask assigned
while the device queue interrupts are spread out over the possible CPUs.

Treating the general interrupts as managed is both a limitation and under
certain circumstances a bug. Assume the following situation:

 default_irq_affinity = 4..7

So if CPUs 4-7 are offlined, then the core code will shut down the device
management interrupts because the last CPU in their affinity mask went
offline.

It's also a limitation because it's desired to allow manual placement of
the general device interrupts for various reasons. If they are marked
managed then the interrupt affinity setting from both user and kernel space
is disabled.

To remedy that situation it's required to convey more information than the
cpumasks through various interfaces related to interrupt descriptor
allocation.

Instead of adding yet another argument, create a new data structure
'irq_affinity_desc' which for now just contains the cpumask. This struct
can be expanded to convey auxilliary information in the next step.

No functional change, just preparatory work.

[ tglx: Simplified logic and clarified changelog ]

Suggested-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Suggested-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
Signed-off-by: Dou Liyang &lt;douliyangs@gmail.com&gt;
Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Cc: linux-pci@vger.kernel.org
Cc: kashyap.desai@broadcom.com
Cc: shivasharan.srikanteshwara@broadcom.com
Cc: sumit.saxena@broadcom.com
Cc: ming.lei@redhat.com
Cc: hch@lst.de
Cc: douliyang1@huawei.com
Link: https://lkml.kernel.org/r/20181204155122.6327-2-douliyangs@gmail.com

</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The interrupt affinity management uses straight cpumask pointers to convey
the automatically assigned affinity masks for managed interrupts. The core
interrupt descriptor allocation also decides based on the pointer being non
NULL whether an interrupt is managed or not.

Devices which use managed interrupts usually have two classes of
interrupts:

  - Interrupts for multiple device queues
  - Interrupts for general device management

Currently both classes are treated the same way, i.e. as managed
interrupts. The general interrupts get the default affinity mask assigned
while the device queue interrupts are spread out over the possible CPUs.

Treating the general interrupts as managed is both a limitation and under
certain circumstances a bug. Assume the following situation:

 default_irq_affinity = 4..7

So if CPUs 4-7 are offlined, then the core code will shut down the device
management interrupts because the last CPU in their affinity mask went
offline.

It's also a limitation because it's desired to allow manual placement of
the general device interrupts for various reasons. If they are marked
managed then the interrupt affinity setting from both user and kernel space
is disabled.

To remedy that situation it's required to convey more information than the
cpumasks through various interfaces related to interrupt descriptor
allocation.

Instead of adding yet another argument, create a new data structure
'irq_affinity_desc' which for now just contains the cpumask. This struct
can be expanded to convey auxilliary information in the next step.

No functional change, just preparatory work.

[ tglx: Simplified logic and clarified changelog ]

Suggested-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Suggested-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
Signed-off-by: Dou Liyang &lt;douliyangs@gmail.com&gt;
Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Cc: linux-pci@vger.kernel.org
Cc: kashyap.desai@broadcom.com
Cc: shivasharan.srikanteshwara@broadcom.com
Cc: sumit.saxena@broadcom.com
Cc: ming.lei@redhat.com
Cc: hch@lst.de
Cc: douliyang1@huawei.com
Link: https://lkml.kernel.org/r/20181204155122.6327-2-douliyangs@gmail.com

</pre>
</div>
</content>
</entry>
<entry>
<title>genirq/msi: Allow level-triggered MSIs to be exposed by MSI providers</title>
<updated>2018-05-13T13:58:59+00:00</updated>
<author>
<name>Marc Zyngier</name>
<email>marc.zyngier@arm.com</email>
</author>
<published>2018-05-08T12:14:30+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=0be8153cbc2af9a96e9ab8631fc3ba23bb52dbe3'/>
<id>0be8153cbc2af9a96e9ab8631fc3ba23bb52dbe3</id>
<content type='text'>
So far, MSIs have been used to signal edge-triggered interrupts, as
a write is a good model for an edge (you can't "unwrite" something).
On the other hand, routing zillions of wires in an SoC because you
need level interrupts is a bit extreme.

People have come up with a variety of schemes to support this, which
involves sending two messages: one to signal the interrupt, and one
to clear it. Since the kernel cannot represent this, we've ended up
with side-band mechanisms that are pretty awful.

Instead, let's acknoledge the requirement, and ensure that, under the
right circumstances, the irq_compose_msg and irq_write_msg can take
as a parameter an array of two messages instead of a pointer to a
single one. We also add some checking that the compose method only
clobbers the second message if the MSI domain has been created with
the MSI_FLAG_LEVEL_CAPABLE flags.

Signed-off-by: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Cc: Rob Herring &lt;robh@kernel.org&gt;
Cc: Jason Cooper &lt;jason@lakedaemon.net&gt;
Cc: Ard Biesheuvel &lt;ard.biesheuvel@linaro.org&gt;
Cc: Srinivas Kandagatla &lt;srinivas.kandagatla@linaro.org&gt;
Cc: Thomas Petazzoni &lt;thomas.petazzoni@bootlin.com&gt;
Cc: Miquel Raynal &lt;miquel.raynal@bootlin.com&gt;
Link: https://lkml.kernel.org/r/20180508121438.11301-2-marc.zyngier@arm.com

</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
So far, MSIs have been used to signal edge-triggered interrupts, as
a write is a good model for an edge (you can't "unwrite" something).
On the other hand, routing zillions of wires in an SoC because you
need level interrupts is a bit extreme.

People have come up with a variety of schemes to support this, which
involves sending two messages: one to signal the interrupt, and one
to clear it. Since the kernel cannot represent this, we've ended up
with side-band mechanisms that are pretty awful.

Instead, let's acknoledge the requirement, and ensure that, under the
right circumstances, the irq_compose_msg and irq_write_msg can take
as a parameter an array of two messages instead of a pointer to a
single one. We also add some checking that the compose method only
clobbers the second message if the MSI domain has been created with
the MSI_FLAG_LEVEL_CAPABLE flags.

Signed-off-by: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Cc: Rob Herring &lt;robh@kernel.org&gt;
Cc: Jason Cooper &lt;jason@lakedaemon.net&gt;
Cc: Ard Biesheuvel &lt;ard.biesheuvel@linaro.org&gt;
Cc: Srinivas Kandagatla &lt;srinivas.kandagatla@linaro.org&gt;
Cc: Thomas Petazzoni &lt;thomas.petazzoni@bootlin.com&gt;
Cc: Miquel Raynal &lt;miquel.raynal@bootlin.com&gt;
Link: https://lkml.kernel.org/r/20180508121438.11301-2-marc.zyngier@arm.com

</pre>
</div>
</content>
</entry>
<entry>
<title>genirq: Add missing SPDX identifiers</title>
<updated>2018-03-20T13:23:28+00:00</updated>
<author>
<name>Thomas Gleixner</name>
<email>tglx@linutronix.de</email>
</author>
<published>2018-03-14T21:15:19+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=52a65ff5603e685e9b19c2e108b3f0826dc7a86b'/>
<id>52a65ff5603e685e9b19c2e108b3f0826dc7a86b</id>
<content type='text'>
Add SPDX identifiers to files

 - which contain an explicit license boiler plate or reference

 - which do not contain a license reference and were not updated in the
   initial SPDX conversion because the license was deduced by the scanners
   via EXPORT_SYMBOL_GPL as GPL2.0 only.

[ tglx: Moved adding identifiers from the patch which removes the
  	references/boilerplate ]

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Cc: Kate Stewart &lt;kstewart@linuxfoundation.org&gt;
Cc: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
Cc: Philippe Ombredanne &lt;pombredanne@nexb.com&gt;
Link: https://lkml.kernel.org/r/20180314212030.668321222@linutronix.de

</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add SPDX identifiers to files

 - which contain an explicit license boiler plate or reference

 - which do not contain a license reference and were not updated in the
   initial SPDX conversion because the license was deduced by the scanners
   via EXPORT_SYMBOL_GPL as GPL2.0 only.

[ tglx: Moved adding identifiers from the patch which removes the
  	references/boilerplate ]

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Cc: Kate Stewart &lt;kstewart@linuxfoundation.org&gt;
Cc: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
Cc: Philippe Ombredanne &lt;pombredanne@nexb.com&gt;
Link: https://lkml.kernel.org/r/20180314212030.668321222@linutronix.de

</pre>
</div>
</content>
</entry>
<entry>
<title>genirq: Cleanup top of file comments</title>
<updated>2018-03-20T13:23:27+00:00</updated>
<author>
<name>Thomas Gleixner</name>
<email>tglx@linutronix.de</email>
</author>
<published>2018-03-14T21:15:16+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=99bfce5db9c071800bdc7e9658a68e6d11aeecf6'/>
<id>99bfce5db9c071800bdc7e9658a68e6d11aeecf6</id>
<content type='text'>
Remove pointless references to the file name itself and condense the
information so it wastes less space.

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Acked-by: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
Cc: Kate Stewart &lt;kstewart@linuxfoundation.org&gt;
Cc: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
Cc: Philippe Ombredanne &lt;pombredanne@nexb.com&gt;
Link: https://lkml.kernel.org/r/20180314212030.412095827@linutronix.de

</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Remove pointless references to the file name itself and condense the
information so it wastes less space.

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Acked-by: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
Cc: Kate Stewart &lt;kstewart@linuxfoundation.org&gt;
Cc: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
Cc: Philippe Ombredanne &lt;pombredanne@nexb.com&gt;
Link: https://lkml.kernel.org/r/20180314212030.412095827@linutronix.de

</pre>
</div>
</content>
</entry>
<entry>
<title>genirq/msi, x86/vector: Prevent reservation mode for non maskable MSI</title>
<updated>2017-12-29T20:13:05+00:00</updated>
<author>
<name>Thomas Gleixner</name>
<email>tglx@linutronix.de</email>
</author>
<published>2017-12-29T09:47:22+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=bc976233a872c0f20f018fb1e89264a541584e25'/>
<id>bc976233a872c0f20f018fb1e89264a541584e25</id>
<content type='text'>
The new reservation mode for interrupts assigns a dummy vector when the
interrupt is allocated and assigns a real vector when the interrupt is
requested. The reservation mode prevents vector pressure when devices with
a large amount of queues/interrupts are initialized, but only a minimal
subset of those queues/interrupts is actually used.

This mode has an issue with MSI interrupts which cannot be masked. If the
driver is not careful or the hardware emits an interrupt before the device
irq is requestd by the driver then the interrupt ends up on the dummy
vector as a spurious interrupt which can cause malfunction of the device or
in the worst case a lockup of the machine.

Change the logic for the reservation mode so that the early activation of
MSI interrupts checks whether:

 - the device is a PCI/MSI device
 - the reservation mode of the underlying irqdomain is activated
 - PCI/MSI masking is globally enabled
 - the PCI/MSI device uses either MSI-X, which supports masking, or
   MSI with the maskbit supported.

If one of those conditions is false, then clear the reservation mode flag
in the irq data of the interrupt and invoke irq_domain_activate_irq() with
the reserve argument cleared. In the x86 vector code, clear the can_reserve
flag in the vector allocation data so a subsequent free_irq() won't create
the same situation again. The interrupt stays assigned to a real vector
until pci_disable_msi() is invoked and all allocations are undone.

Fixes: 4900be83602b ("x86/vector/msi: Switch to global reservation mode")
Reported-by: Alexandru Chirvasitu &lt;achirvasub@gmail.com&gt;
Reported-by: Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;
Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Tested-by: Alexandru Chirvasitu &lt;achirvasub@gmail.com&gt;
Tested-by: Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;
Cc: Dou Liyang &lt;douly.fnst@cn.fujitsu.com&gt;
Cc: Pavel Machek &lt;pavel@ucw.cz&gt;
Cc: Maciej W. Rozycki &lt;macro@linux-mips.org&gt;
Cc: Mikael Pettersson &lt;mikpelinux@gmail.com&gt;
Cc: Josh Poulson &lt;jopoulso@microsoft.com&gt;
Cc: Mihai Costache &lt;v-micos@microsoft.com&gt;
Cc: Stephen Hemminger &lt;sthemmin@microsoft.com&gt;
Cc: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
Cc: linux-pci@vger.kernel.org
Cc: Haiyang Zhang &lt;haiyangz@microsoft.com&gt;
Cc: Dexuan Cui &lt;decui@microsoft.com&gt;
Cc: Simon Xiao &lt;sixiao@microsoft.com&gt;
Cc: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
Cc: Jork Loeser &lt;Jork.Loeser@microsoft.com&gt;
Cc: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
Cc: devel@linuxdriverproject.org
Cc: KY Srinivasan &lt;kys@microsoft.com&gt;
Cc: Alan Cox &lt;alan@linux.intel.com&gt;
Cc: Sakari Ailus &lt;sakari.ailus@intel.com&gt;,
Cc: linux-media@vger.kernel.org
Link: https://lkml.kernel.org/r/alpine.DEB.2.20.1712291406420.1899@nanos
Link: https://lkml.kernel.org/r/alpine.DEB.2.20.1712291409460.1899@nanos
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The new reservation mode for interrupts assigns a dummy vector when the
interrupt is allocated and assigns a real vector when the interrupt is
requested. The reservation mode prevents vector pressure when devices with
a large amount of queues/interrupts are initialized, but only a minimal
subset of those queues/interrupts is actually used.

This mode has an issue with MSI interrupts which cannot be masked. If the
driver is not careful or the hardware emits an interrupt before the device
irq is requestd by the driver then the interrupt ends up on the dummy
vector as a spurious interrupt which can cause malfunction of the device or
in the worst case a lockup of the machine.

Change the logic for the reservation mode so that the early activation of
MSI interrupts checks whether:

 - the device is a PCI/MSI device
 - the reservation mode of the underlying irqdomain is activated
 - PCI/MSI masking is globally enabled
 - the PCI/MSI device uses either MSI-X, which supports masking, or
   MSI with the maskbit supported.

If one of those conditions is false, then clear the reservation mode flag
in the irq data of the interrupt and invoke irq_domain_activate_irq() with
the reserve argument cleared. In the x86 vector code, clear the can_reserve
flag in the vector allocation data so a subsequent free_irq() won't create
the same situation again. The interrupt stays assigned to a real vector
until pci_disable_msi() is invoked and all allocations are undone.

Fixes: 4900be83602b ("x86/vector/msi: Switch to global reservation mode")
Reported-by: Alexandru Chirvasitu &lt;achirvasub@gmail.com&gt;
Reported-by: Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;
Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Tested-by: Alexandru Chirvasitu &lt;achirvasub@gmail.com&gt;
Tested-by: Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;
Cc: Dou Liyang &lt;douly.fnst@cn.fujitsu.com&gt;
Cc: Pavel Machek &lt;pavel@ucw.cz&gt;
Cc: Maciej W. Rozycki &lt;macro@linux-mips.org&gt;
Cc: Mikael Pettersson &lt;mikpelinux@gmail.com&gt;
Cc: Josh Poulson &lt;jopoulso@microsoft.com&gt;
Cc: Mihai Costache &lt;v-micos@microsoft.com&gt;
Cc: Stephen Hemminger &lt;sthemmin@microsoft.com&gt;
Cc: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
Cc: linux-pci@vger.kernel.org
Cc: Haiyang Zhang &lt;haiyangz@microsoft.com&gt;
Cc: Dexuan Cui &lt;decui@microsoft.com&gt;
Cc: Simon Xiao &lt;sixiao@microsoft.com&gt;
Cc: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
Cc: Jork Loeser &lt;Jork.Loeser@microsoft.com&gt;
Cc: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
Cc: devel@linuxdriverproject.org
Cc: KY Srinivasan &lt;kys@microsoft.com&gt;
Cc: Alan Cox &lt;alan@linux.intel.com&gt;
Cc: Sakari Ailus &lt;sakari.ailus@intel.com&gt;,
Cc: linux-media@vger.kernel.org
Link: https://lkml.kernel.org/r/alpine.DEB.2.20.1712291406420.1899@nanos
Link: https://lkml.kernel.org/r/alpine.DEB.2.20.1712291409460.1899@nanos
</pre>
</div>
</content>
</entry>
<entry>
<title>genirq/msi: Handle reactivation only on success</title>
<updated>2017-12-29T20:13:04+00:00</updated>
<author>
<name>Thomas Gleixner</name>
<email>tglx@linutronix.de</email>
</author>
<published>2017-12-29T09:42:10+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=da5dd9e854d2edd6b02ebfe28583052f922104da'/>
<id>da5dd9e854d2edd6b02ebfe28583052f922104da</id>
<content type='text'>
When analyzing the fallout of the x86 vector allocation rework it turned
out that the error handling in msi_domain_alloc_irqs() is broken.

If MSI_FLAG_MUST_REACTIVATE is set for a MSI domain then it clears the
activation flag for a successfully initialized msi descriptor. If a
subsequent initialization fails then the error handling code path does not
deactivate the interrupt because the activation flag got cleared.

Move the clearing of the activation flag outside of the initialization loop
so that an eventual failure can be cleaned up correctly.

Fixes: 22d0b12f3560 ("genirq/irqdomain: Add force reactivation flag to irq domains")
Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Tested-by: Alexandru Chirvasitu &lt;achirvasub@gmail.com&gt;
Tested-by: Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;
Cc: Dou Liyang &lt;douly.fnst@cn.fujitsu.com&gt;
Cc: Pavel Machek &lt;pavel@ucw.cz&gt;
Cc: Maciej W. Rozycki &lt;macro@linux-mips.org&gt;
Cc: Mikael Pettersson &lt;mikpelinux@gmail.com&gt;
Cc: Josh Poulson &lt;jopoulso@microsoft.com&gt;
Cc: Mihai Costache &lt;v-micos@microsoft.com&gt;
Cc: Stephen Hemminger &lt;sthemmin@microsoft.com&gt;
Cc: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
Cc: linux-pci@vger.kernel.org
Cc: Haiyang Zhang &lt;haiyangz@microsoft.com&gt;
Cc: Dexuan Cui &lt;decui@microsoft.com&gt;
Cc: Simon Xiao &lt;sixiao@microsoft.com&gt;
Cc: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
Cc: Jork Loeser &lt;Jork.Loeser@microsoft.com&gt;
Cc: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
Cc: devel@linuxdriverproject.org
Cc: KY Srinivasan &lt;kys@microsoft.com&gt;
Cc: Alan Cox &lt;alan@linux.intel.com&gt;
Cc: Sakari Ailus &lt;sakari.ailus@intel.com&gt;,
Cc: linux-media@vger.kernel.org


</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
When analyzing the fallout of the x86 vector allocation rework it turned
out that the error handling in msi_domain_alloc_irqs() is broken.

If MSI_FLAG_MUST_REACTIVATE is set for a MSI domain then it clears the
activation flag for a successfully initialized msi descriptor. If a
subsequent initialization fails then the error handling code path does not
deactivate the interrupt because the activation flag got cleared.

Move the clearing of the activation flag outside of the initialization loop
so that an eventual failure can be cleaned up correctly.

Fixes: 22d0b12f3560 ("genirq/irqdomain: Add force reactivation flag to irq domains")
Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Tested-by: Alexandru Chirvasitu &lt;achirvasub@gmail.com&gt;
Tested-by: Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;
Cc: Dou Liyang &lt;douly.fnst@cn.fujitsu.com&gt;
Cc: Pavel Machek &lt;pavel@ucw.cz&gt;
Cc: Maciej W. Rozycki &lt;macro@linux-mips.org&gt;
Cc: Mikael Pettersson &lt;mikpelinux@gmail.com&gt;
Cc: Josh Poulson &lt;jopoulso@microsoft.com&gt;
Cc: Mihai Costache &lt;v-micos@microsoft.com&gt;
Cc: Stephen Hemminger &lt;sthemmin@microsoft.com&gt;
Cc: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
Cc: linux-pci@vger.kernel.org
Cc: Haiyang Zhang &lt;haiyangz@microsoft.com&gt;
Cc: Dexuan Cui &lt;decui@microsoft.com&gt;
Cc: Simon Xiao &lt;sixiao@microsoft.com&gt;
Cc: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
Cc: Jork Loeser &lt;Jork.Loeser@microsoft.com&gt;
Cc: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
Cc: devel@linuxdriverproject.org
Cc: KY Srinivasan &lt;kys@microsoft.com&gt;
Cc: Alan Cox &lt;alan@linux.intel.com&gt;
Cc: Sakari Ailus &lt;sakari.ailus@intel.com&gt;,
Cc: linux-media@vger.kernel.org


</pre>
</div>
</content>
</entry>
<entry>
<title>genirq/irqdomain: Add force reactivation flag to irq domains</title>
<updated>2017-09-25T18:38:25+00:00</updated>
<author>
<name>Thomas Gleixner</name>
<email>tglx@linutronix.de</email>
</author>
<published>2017-09-13T21:29:13+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=22d0b12f3560d3b3264ee79faa1c05a5060fb916'/>
<id>22d0b12f3560d3b3264ee79faa1c05a5060fb916</id>
<content type='text'>
Allow irqdomains to tell the core code, that after early activation the
interrupt needs to be reactivated at request_irq() time.

This allows reservation of vectors at early activation time and actual
vector assignment at request_irq() time.

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Tested-by: Juergen Gross &lt;jgross@suse.com&gt;
Tested-by: Yu Chen &lt;yu.c.chen@intel.com&gt;
Acked-by: Juergen Gross &lt;jgross@suse.com&gt;
Cc: Boris Ostrovsky &lt;boris.ostrovsky@oracle.com&gt;
Cc: Tony Luck &lt;tony.luck@intel.com&gt;
Cc: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
Cc: Alok Kataria &lt;akataria@vmware.com&gt;
Cc: Joerg Roedel &lt;joro@8bytes.org&gt;
Cc: "Rafael J. Wysocki" &lt;rjw@rjwysocki.net&gt;
Cc: Steven Rostedt &lt;rostedt@goodmis.org&gt;
Cc: Christoph Hellwig &lt;hch@lst.de&gt;
Cc: Peter Zijlstra &lt;peterz@infradead.org&gt;
Cc: Borislav Petkov &lt;bp@alien8.de&gt;
Cc: Paolo Bonzini &lt;pbonzini@redhat.com&gt;
Cc: Rui Zhang &lt;rui.zhang@intel.com&gt;
Cc: "K. Y. Srinivasan" &lt;kys@microsoft.com&gt;
Cc: Arjan van de Ven &lt;arjan@linux.intel.com&gt;
Cc: Dan Williams &lt;dan.j.williams@intel.com&gt;
Cc: Len Brown &lt;lenb@kernel.org&gt;
Link: https://lkml.kernel.org/r/20170913213153.106242536@linutronix.de

</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Allow irqdomains to tell the core code, that after early activation the
interrupt needs to be reactivated at request_irq() time.

This allows reservation of vectors at early activation time and actual
vector assignment at request_irq() time.

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Tested-by: Juergen Gross &lt;jgross@suse.com&gt;
Tested-by: Yu Chen &lt;yu.c.chen@intel.com&gt;
Acked-by: Juergen Gross &lt;jgross@suse.com&gt;
Cc: Boris Ostrovsky &lt;boris.ostrovsky@oracle.com&gt;
Cc: Tony Luck &lt;tony.luck@intel.com&gt;
Cc: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
Cc: Alok Kataria &lt;akataria@vmware.com&gt;
Cc: Joerg Roedel &lt;joro@8bytes.org&gt;
Cc: "Rafael J. Wysocki" &lt;rjw@rjwysocki.net&gt;
Cc: Steven Rostedt &lt;rostedt@goodmis.org&gt;
Cc: Christoph Hellwig &lt;hch@lst.de&gt;
Cc: Peter Zijlstra &lt;peterz@infradead.org&gt;
Cc: Borislav Petkov &lt;bp@alien8.de&gt;
Cc: Paolo Bonzini &lt;pbonzini@redhat.com&gt;
Cc: Rui Zhang &lt;rui.zhang@intel.com&gt;
Cc: "K. Y. Srinivasan" &lt;kys@microsoft.com&gt;
Cc: Arjan van de Ven &lt;arjan@linux.intel.com&gt;
Cc: Dan Williams &lt;dan.j.williams@intel.com&gt;
Cc: Len Brown &lt;lenb@kernel.org&gt;
Link: https://lkml.kernel.org/r/20170913213153.106242536@linutronix.de

</pre>
</div>
</content>
</entry>
<entry>
<title>genirq/irqdomain: Propagate early activation</title>
<updated>2017-09-25T18:38:25+00:00</updated>
<author>
<name>Thomas Gleixner</name>
<email>tglx@linutronix.de</email>
</author>
<published>2017-09-13T21:29:12+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=42e1cc2dc5b698181ab1ffb7972bd880230c506e'/>
<id>42e1cc2dc5b698181ab1ffb7972bd880230c506e</id>
<content type='text'>
Propagate the early activation mode to the irqdomain activate()
callbacks. This is required for the upcoming reservation, late vector
assignment scheme, so that the early activation call can act accordingly.

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Tested-by: Juergen Gross &lt;jgross@suse.com&gt;
Tested-by: Yu Chen &lt;yu.c.chen@intel.com&gt;
Acked-by: Juergen Gross &lt;jgross@suse.com&gt;
Cc: Boris Ostrovsky &lt;boris.ostrovsky@oracle.com&gt;
Cc: Tony Luck &lt;tony.luck@intel.com&gt;
Cc: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
Cc: Alok Kataria &lt;akataria@vmware.com&gt;
Cc: Joerg Roedel &lt;joro@8bytes.org&gt;
Cc: "Rafael J. Wysocki" &lt;rjw@rjwysocki.net&gt;
Cc: Steven Rostedt &lt;rostedt@goodmis.org&gt;
Cc: Christoph Hellwig &lt;hch@lst.de&gt;
Cc: Peter Zijlstra &lt;peterz@infradead.org&gt;
Cc: Borislav Petkov &lt;bp@alien8.de&gt;
Cc: Paolo Bonzini &lt;pbonzini@redhat.com&gt;
Cc: Rui Zhang &lt;rui.zhang@intel.com&gt;
Cc: "K. Y. Srinivasan" &lt;kys@microsoft.com&gt;
Cc: Arjan van de Ven &lt;arjan@linux.intel.com&gt;
Cc: Dan Williams &lt;dan.j.williams@intel.com&gt;
Cc: Len Brown &lt;lenb@kernel.org&gt;
Link: https://lkml.kernel.org/r/20170913213153.028353660@linutronix.de

</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Propagate the early activation mode to the irqdomain activate()
callbacks. This is required for the upcoming reservation, late vector
assignment scheme, so that the early activation call can act accordingly.

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Tested-by: Juergen Gross &lt;jgross@suse.com&gt;
Tested-by: Yu Chen &lt;yu.c.chen@intel.com&gt;
Acked-by: Juergen Gross &lt;jgross@suse.com&gt;
Cc: Boris Ostrovsky &lt;boris.ostrovsky@oracle.com&gt;
Cc: Tony Luck &lt;tony.luck@intel.com&gt;
Cc: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
Cc: Alok Kataria &lt;akataria@vmware.com&gt;
Cc: Joerg Roedel &lt;joro@8bytes.org&gt;
Cc: "Rafael J. Wysocki" &lt;rjw@rjwysocki.net&gt;
Cc: Steven Rostedt &lt;rostedt@goodmis.org&gt;
Cc: Christoph Hellwig &lt;hch@lst.de&gt;
Cc: Peter Zijlstra &lt;peterz@infradead.org&gt;
Cc: Borislav Petkov &lt;bp@alien8.de&gt;
Cc: Paolo Bonzini &lt;pbonzini@redhat.com&gt;
Cc: Rui Zhang &lt;rui.zhang@intel.com&gt;
Cc: "K. Y. Srinivasan" &lt;kys@microsoft.com&gt;
Cc: Arjan van de Ven &lt;arjan@linux.intel.com&gt;
Cc: Dan Williams &lt;dan.j.williams@intel.com&gt;
Cc: Len Brown &lt;lenb@kernel.org&gt;
Link: https://lkml.kernel.org/r/20170913213153.028353660@linutronix.de

</pre>
</div>
</content>
</entry>
<entry>
<title>genirq/irqdomain: Allow irq_domain_activate_irq() to fail</title>
<updated>2017-09-25T18:38:24+00:00</updated>
<author>
<name>Thomas Gleixner</name>
<email>tglx@linutronix.de</email>
</author>
<published>2017-09-13T21:29:11+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=bb9b428a5c832d7abb494fbabac37c515c01c6c4'/>
<id>bb9b428a5c832d7abb494fbabac37c515c01c6c4</id>
<content type='text'>
Allow irq_domain_activate_irq() to fail. This is required to support a
reservation and late vector assignment scheme.

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Tested-by: Juergen Gross &lt;jgross@suse.com&gt;
Tested-by: Yu Chen &lt;yu.c.chen@intel.com&gt;
Acked-by: Juergen Gross &lt;jgross@suse.com&gt;
Cc: Boris Ostrovsky &lt;boris.ostrovsky@oracle.com&gt;
Cc: Tony Luck &lt;tony.luck@intel.com&gt;
Cc: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
Cc: Alok Kataria &lt;akataria@vmware.com&gt;
Cc: Joerg Roedel &lt;joro@8bytes.org&gt;
Cc: "Rafael J. Wysocki" &lt;rjw@rjwysocki.net&gt;
Cc: Steven Rostedt &lt;rostedt@goodmis.org&gt;
Cc: Christoph Hellwig &lt;hch@lst.de&gt;
Cc: Peter Zijlstra &lt;peterz@infradead.org&gt;
Cc: Borislav Petkov &lt;bp@alien8.de&gt;
Cc: Paolo Bonzini &lt;pbonzini@redhat.com&gt;
Cc: Rui Zhang &lt;rui.zhang@intel.com&gt;
Cc: "K. Y. Srinivasan" &lt;kys@microsoft.com&gt;
Cc: Arjan van de Ven &lt;arjan@linux.intel.com&gt;
Cc: Dan Williams &lt;dan.j.williams@intel.com&gt;
Cc: Len Brown &lt;lenb@kernel.org&gt;
Link: https://lkml.kernel.org/r/20170913213152.933882227@linutronix.de

</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Allow irq_domain_activate_irq() to fail. This is required to support a
reservation and late vector assignment scheme.

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Tested-by: Juergen Gross &lt;jgross@suse.com&gt;
Tested-by: Yu Chen &lt;yu.c.chen@intel.com&gt;
Acked-by: Juergen Gross &lt;jgross@suse.com&gt;
Cc: Boris Ostrovsky &lt;boris.ostrovsky@oracle.com&gt;
Cc: Tony Luck &lt;tony.luck@intel.com&gt;
Cc: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
Cc: Alok Kataria &lt;akataria@vmware.com&gt;
Cc: Joerg Roedel &lt;joro@8bytes.org&gt;
Cc: "Rafael J. Wysocki" &lt;rjw@rjwysocki.net&gt;
Cc: Steven Rostedt &lt;rostedt@goodmis.org&gt;
Cc: Christoph Hellwig &lt;hch@lst.de&gt;
Cc: Peter Zijlstra &lt;peterz@infradead.org&gt;
Cc: Borislav Petkov &lt;bp@alien8.de&gt;
Cc: Paolo Bonzini &lt;pbonzini@redhat.com&gt;
Cc: Rui Zhang &lt;rui.zhang@intel.com&gt;
Cc: "K. Y. Srinivasan" &lt;kys@microsoft.com&gt;
Cc: Arjan van de Ven &lt;arjan@linux.intel.com&gt;
Cc: Dan Williams &lt;dan.j.williams@intel.com&gt;
Cc: Len Brown &lt;lenb@kernel.org&gt;
Link: https://lkml.kernel.org/r/20170913213152.933882227@linutronix.de

</pre>
</div>
</content>
</entry>
<entry>
<title>genirq/irqdomain: Update irq_domain_ops.activate() signature</title>
<updated>2017-09-25T18:38:24+00:00</updated>
<author>
<name>Thomas Gleixner</name>
<email>tglx@linutronix.de</email>
</author>
<published>2017-09-13T21:29:10+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=72491643469aab736536ae71dcd199b19dabd891'/>
<id>72491643469aab736536ae71dcd199b19dabd891</id>
<content type='text'>
The irq_domain_ops.activate() callback has no return value and no way to
tell the function that the activation is early.

The upcoming changes to support a reservation scheme which allows to assign
interrupt vectors on x86 only when the interrupt is actually requested
requires:

  - A return value, so activation can fail at request_irq() time
  
  - Information that the activate invocation is early, i.e. before
    request_irq().

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Tested-by: Juergen Gross &lt;jgross@suse.com&gt;
Tested-by: Yu Chen &lt;yu.c.chen@intel.com&gt;
Acked-by: Juergen Gross &lt;jgross@suse.com&gt;
Cc: Boris Ostrovsky &lt;boris.ostrovsky@oracle.com&gt;
Cc: Tony Luck &lt;tony.luck@intel.com&gt;
Cc: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
Cc: Alok Kataria &lt;akataria@vmware.com&gt;
Cc: Joerg Roedel &lt;joro@8bytes.org&gt;
Cc: "Rafael J. Wysocki" &lt;rjw@rjwysocki.net&gt;
Cc: Steven Rostedt &lt;rostedt@goodmis.org&gt;
Cc: Christoph Hellwig &lt;hch@lst.de&gt;
Cc: Peter Zijlstra &lt;peterz@infradead.org&gt;
Cc: Borislav Petkov &lt;bp@alien8.de&gt;
Cc: Paolo Bonzini &lt;pbonzini@redhat.com&gt;
Cc: Rui Zhang &lt;rui.zhang@intel.com&gt;
Cc: "K. Y. Srinivasan" &lt;kys@microsoft.com&gt;
Cc: Arjan van de Ven &lt;arjan@linux.intel.com&gt;
Cc: Dan Williams &lt;dan.j.williams@intel.com&gt;
Cc: Len Brown &lt;lenb@kernel.org&gt;
Link: https://lkml.kernel.org/r/20170913213152.848490816@linutronix.de

</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The irq_domain_ops.activate() callback has no return value and no way to
tell the function that the activation is early.

The upcoming changes to support a reservation scheme which allows to assign
interrupt vectors on x86 only when the interrupt is actually requested
requires:

  - A return value, so activation can fail at request_irq() time
  
  - Information that the activate invocation is early, i.e. before
    request_irq().

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Tested-by: Juergen Gross &lt;jgross@suse.com&gt;
Tested-by: Yu Chen &lt;yu.c.chen@intel.com&gt;
Acked-by: Juergen Gross &lt;jgross@suse.com&gt;
Cc: Boris Ostrovsky &lt;boris.ostrovsky@oracle.com&gt;
Cc: Tony Luck &lt;tony.luck@intel.com&gt;
Cc: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
Cc: Alok Kataria &lt;akataria@vmware.com&gt;
Cc: Joerg Roedel &lt;joro@8bytes.org&gt;
Cc: "Rafael J. Wysocki" &lt;rjw@rjwysocki.net&gt;
Cc: Steven Rostedt &lt;rostedt@goodmis.org&gt;
Cc: Christoph Hellwig &lt;hch@lst.de&gt;
Cc: Peter Zijlstra &lt;peterz@infradead.org&gt;
Cc: Borislav Petkov &lt;bp@alien8.de&gt;
Cc: Paolo Bonzini &lt;pbonzini@redhat.com&gt;
Cc: Rui Zhang &lt;rui.zhang@intel.com&gt;
Cc: "K. Y. Srinivasan" &lt;kys@microsoft.com&gt;
Cc: Arjan van de Ven &lt;arjan@linux.intel.com&gt;
Cc: Dan Williams &lt;dan.j.williams@intel.com&gt;
Cc: Len Brown &lt;lenb@kernel.org&gt;
Link: https://lkml.kernel.org/r/20170913213152.848490816@linutronix.de

</pre>
</div>
</content>
</entry>
</feed>
