linux-toradex.git/sound/soc/sof/intel/shim.h, branch v6.5-rc4 Linux kernel for Apalis and Colibri modules ASoC: SOF: Intel: shim: add enum for ACE 2.0 IP used in LunarLake 2023-05-27T10:36:44+00:00 Pierre-Louis Bossart pierre-louis.bossart@linux.intel.com 2023-05-15T07:10:17+00:00 4f5706f16c99d70a610eaade8273ea99152d2959 Add the new enum needed for SoundWire IP selection. The LunarLake PCI descriptors and DSP parts will be added at a later time. Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Reviewed-by: Rander Wang <rander.wang@intel.com> Reviewed-by: Péter Ujfalusi <peter.ujfalusi@linux.intel.com> Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com> Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com> Acked-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20230515071042.2038-2-yung-chuan.liao@linux.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org> 
Add the new enum needed for SoundWire IP selection. The LunarLake PCI
descriptors and DSP parts will be added at a later time.

Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Rander Wang <rander.wang@intel.com>
Reviewed-by: Péter Ujfalusi <peter.ujfalusi@linux.intel.com>
Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Acked-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20230515071042.2038-2-yung-chuan.liao@linux.intel.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
ASoC: SOF: Intel: hda: add callback to check SoundWire lcount information 2022-11-23T15:32:05+00:00 Pierre-Louis Bossart pierre-louis.bossart@linux.intel.com 2022-11-11T04:26:50+00:00 625339caaea15c0e69d833227652d2f5b6e365cc The number of links is stored in different registers depending on the IP version, add sdw_check_lcount() callback. This callback only checks that the number of links supported in hardware is compatible with the number of links exposed in ACPI _DSD properties. Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Reviewed-by: Péter Ujfalusi <peter.ujfalusi@linux.intel.com> Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com> Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com> Link: https://lore.kernel.org/r/20221111042653.45520-6-yung-chuan.liao@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org> 
The number of links is stored in different registers depending on the
IP version, add sdw_check_lcount() callback. This callback only checks
that the number of links supported in hardware is compatible with the
number of links exposed in ACPI _DSD properties.

Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Péter Ujfalusi <peter.ujfalusi@linux.intel.com>
Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Link: https://lore.kernel.org/r/20221111042653.45520-6-yung-chuan.liao@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
ASoC: SOF: Intel: hda: add per-chip enable_sdw_irq() callback 2022-11-23T15:32:02+00:00 Pierre-Louis Bossart pierre-louis.bossart@linux.intel.com 2022-11-11T04:26:47+00:00 8ebc90741e96646af7320336ac4433eea175390a Different generations of Intel hardware rely on different programming sequences to enable SoundWire IP. In existing hardware, the SoundWire interrupt is enabled with a register field in the DSP register space. With HDaudio multi-link extensions registers, the SoundWire interrupt will be enabled with a generic interrupt enable field in LCTL, without any dependency on the DSP being enabled. Add a per-chip callback following the example of the check_sdw_irq() model already upstream. Note that the callback is not populated yet for MeteorLake (MTL) since the interrupts are already enabled in the init. A follow-up patch will move the functionality to this callback after a couple of cleanups. Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Reviewed-by: Péter Ujfalusi <peter.ujfalusi@linux.intel.com> Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com> Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com> Link: https://lore.kernel.org/r/20221111042653.45520-3-yung-chuan.liao@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org> 
Different generations of Intel hardware rely on different programming
sequences to enable SoundWire IP. In existing hardware, the SoundWire
interrupt is enabled with a register field in the DSP register
space. With HDaudio multi-link extensions registers, the SoundWire
interrupt will be enabled with a generic interrupt enable field in
LCTL, without any dependency on the DSP being enabled.

Add a per-chip callback following the example of the check_sdw_irq()
model already upstream.

Note that the callback is not populated yet for MeteorLake (MTL) since
the interrupts are already enabled in the init. A follow-up patch will
move the functionality to this callback after a couple of cleanups.

Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Péter Ujfalusi <peter.ujfalusi@linux.intel.com>
Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Link: https://lore.kernel.org/r/20221111042653.45520-3-yung-chuan.liao@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
ASoC: SOF: Intel: add d0i3_offset in chip_info 2022-11-07T17:10:07+00:00 Rander Wang rander.wang@intel.com 2022-11-07T16:41:53+00:00 f8632adc53e25501c74f25794cddac4dbe3f1c59 MTL has different d0i3 offset compared to cavs platforms. Use d0i3_offset to unify the setting. Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com> Signed-off-by: Rander Wang <rander.wang@intel.com> Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Link: https://lore.kernel.org/r/20221107164154.21925-3-pierre-louis.bossart@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org> 
MTL has different d0i3 offset compared to cavs platforms.
Use d0i3_offset to unify the setting.

Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Signed-off-by: Rander Wang <rander.wang@intel.com>
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Link: https://lore.kernel.org/r/20221107164154.21925-3-pierre-louis.bossart@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
ASoC: SOF: Intel: Add a new op for disabling interrupts 2022-09-23T12:56:16+00:00 Ranjani Sridharan ranjani.sridharan@linux.intel.com 2022-09-22T21:36:39+00:00 423693a6c351f4abb869d1dbf5df7374766aaa1a The sequence for disabling DSP interrupts varies between different IP versions. Signed-off-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com> Reviewed-by: Bard Liao <yung-chuan.liao@linux.intel.com> Reviewed-by: Rander Wang <rander.wang@intel.com> Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Link: https://lore.kernel.org/r/20220922213644.666315-6-ranjani.sridharan@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org> 
The sequence for disabling DSP interrupts varies between different IP
versions.

Signed-off-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Reviewed-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Reviewed-by: Rander Wang <rander.wang@intel.com>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Link: https://lore.kernel.org/r/20220922213644.666315-6-ranjani.sridharan@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
ASoC: SOF: Intel: introduce new op to handle dsp power down 2022-09-23T12:56:12+00:00 Fred Oh fred.oh@linux.intel.com 2022-09-22T21:36:35+00:00 af62eaf2872bf2c381f322c61f7ff751162797f6 DSP core power down sequences are different between cavs platforms and MTL. Signed-off-by: Fred Oh <fred.oh@linux.intel.com> Reviewed-by: Rander Wang <rander.wang@intel.com> Reviewed-by: Bard Liao <yung-chuan.liao@linux.intel.com> Signed-off-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com> Link: https://lore.kernel.org/r/20220922213644.666315-2-ranjani.sridharan@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org> 
DSP core power down sequences are different between cavs platforms and MTL.

Signed-off-by: Fred Oh <fred.oh@linux.intel.com>
Reviewed-by: Rander Wang <rander.wang@intel.com>
Reviewed-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Signed-off-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Link: https://lore.kernel.org/r/20220922213644.666315-2-ranjani.sridharan@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
ASoC: SOF: Intel: Add support for MeteorLake (MTL) 2022-06-15T08:56:57+00:00 Bard Liao yung-chuan.liao@linux.intel.com 2022-06-15T08:43:48+00:00 064520e8aeaa2569f6504a50a37ac801b73656bc Add platform abstraction for the Meteor Lake platform. This platform has significant differences compared to the TGL/ADL generation: it relies on new hardware using the code name 'ACE' and only supports the INTEL_IPC4 protocol and firmware architecture based on the Zephyr RTOS Co-developed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com> Signed-off-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com> Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com> Reviewed-by: Péter Ujfalusi <peter.ujfalusi@linux.intel.com> Reviewed-by: Rander Wang <rander.wang@intel.com> Link: https://lore.kernel.org/r/20220615084348.3489-3-yung-chuan.liao@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org> 
Add platform abstraction for the Meteor Lake platform.

This platform has significant differences compared to the TGL/ADL
generation: it relies on new hardware using the code name 'ACE' and
only supports the INTEL_IPC4 protocol and firmware architecture based
on the Zephyr RTOS

Co-developed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Signed-off-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Reviewed-by: Péter Ujfalusi <peter.ujfalusi@linux.intel.com>
Reviewed-by: Rander Wang <rander.wang@intel.com>
Link: https://lore.kernel.org/r/20220615084348.3489-3-yung-chuan.liao@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
ASoC: SOC: Intel: introduce cl_init callback 2022-06-15T08:56:56+00:00 Bard Liao yung-chuan.liao@linux.intel.com 2022-06-15T08:43:47+00:00 ab222a4aaecfafece1516c775143e1cb9eb31612 The code loader init sequences are different between versions of Intel platforms. Have a cl_init callback allows us to reuse the common code. No function changed. Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com> Reviewed-by: Péter Ujfalusi <peter.ujfalusi@linux.intel.com> Reviewed-by: Rander Wang <rander.wang@intel.com> Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com> Link: https://lore.kernel.org/r/20220615084348.3489-2-yung-chuan.liao@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org> 
The code loader init sequences are different between versions of
Intel platforms. Have a cl_init callback allows us to reuse the
common code.
No function changed.

Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Reviewed-by: Péter Ujfalusi <peter.ujfalusi@linux.intel.com>
Reviewed-by: Rander Wang <rander.wang@intel.com>
Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Link: https://lore.kernel.org/r/20220615084348.3489-2-yung-chuan.liao@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
ASoC: SOF: Intel: add IP identifier 2022-04-19T11:03:46+00:00 Pierre-Louis Bossart pierre-louis.bossart@linux.intel.com 2022-04-14T18:48:17+00:00 03cf7262076f08601108cc896416fc1d66671994 This patch adds an IP identifier for each Intel platform. The identifier will be used to select different code branches or constants. Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Reviewed-by: Péter Ujfalusi <peter.ujfalusi@linux.intel.com> Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com> Link: https://lore.kernel.org/r/20220414184817.362215-16-pierre-louis.bossart@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org> 
This patch adds an IP identifier for each Intel platform. The
identifier will be used to select different code branches or
constants.

Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Péter Ujfalusi <peter.ujfalusi@linux.intel.com>
Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Link: https://lore.kernel.org/r/20220414184817.362215-16-pierre-louis.bossart@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
ASoC: SOF: Intel: hda: Define rom_status_reg in sof_intel_dsp_desc 2022-04-19T11:03:44+00:00 Ranjani Sridharan ranjani.sridharan@linux.intel.com 2022-04-14T18:48:15+00:00 71778f7940f0b496aa1ca1134f3b70b425a59bab Add the rom_status_reg field to struct sof_intel_dsp_desc and define it for HDA platforms. This will be used to check the ROM status during FW boot. Signed-off-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com> Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Reviewed-by: Péter Ujfalusi <peter.ujfalusi@linux.intel.com> Link: https://lore.kernel.org/r/20220414184817.362215-14-pierre-louis.bossart@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org> 
Add the rom_status_reg field to struct sof_intel_dsp_desc and define
it for HDA platforms. This will be used to check the ROM status during
FW boot.

Signed-off-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Péter Ujfalusi <peter.ujfalusi@linux.intel.com>
Link: https://lore.kernel.org/r/20220414184817.362215-14-pierre-louis.bossart@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>