linux-toradex.git/tools/perf/pmu-events, branch master

perf pmu-events: Add API to get metric table name and iterate tables

2026-06-04T14:35:52+00:00

Add name field to struct pmu_metrics_table and populate it in generated
tables. Add pmu_metrics_table__name() to retrieve the name. Add
pmu_metrics_table__for_each_table() to iterate over all known metric
tables.

This will be used to break apart slow metric tests per table.

Assisted-by: Gemini-CLI:Google Gemini 3
Signed-off-by: Ian Rogers 
Cc: Adrian Hunter 
Cc: Alexander Shishkin 
Cc: Ingo Molnar 
Cc: James Clark 
Cc: Jiri Olsa 
Cc: Namhyung Kim 
Cc: Peter Zijlstra 
Signed-off-by: Arnaldo Carvalho de Melo

perf jevents.py: Make generated C code more kernel style

2026-06-04T14:35:32+00:00

Make jevents.py generate C code that complies with formatting tools:

- Add /* clang-format off */ before big_c_string and re-enable it
  after system mapping tables, bypassing large generated tables while
  checking functions and early structs.
- Make comments more human readable and avoid going over 100 character
  line length.
- Fix spaces indentation to tabs in struct/array initializers.
- Fix other checkpatch detected related issues.

Assisted-by: Gemini-CLI:Google Gemini 3
Signed-off-by: Ian Rogers 
Cc: Adrian Hunter 
Cc: Alexander Shishkin 
Cc: Ingo Molnar 
Cc: James Clark 
Cc: Jiri Olsa 
Cc: Namhyung Kim 
Cc: Peter Zijlstra 
Signed-off-by: Arnaldo Carvalho de Melo

perf stat: Use aggr_nr scaling for Intel uncore miss latency metrics

2026-06-04T13:58:47+00:00

Update `metric.py` to support the new `aggr_nr` keyword in the python
metric generator. Replace the usage of `source_count` with `aggr_nr` in
`IntelMissLat` inside `intel_metrics.py` so that uncore latency metrics
(like `lpm_miss_lat`) scale correctly on multi-socket and SNC systems when
aggregated globally.

Additionally, update the validation bypass logic in `CheckEveryEvent()`
inside `metric.py` to whitelist 'cha' and 'uncore' events. This
prevents validation failures when compiling metrics referencing these
PMU-specific uncore events.

Assisted-by: Gemini:gemini-3.1-pro-preview
Signed-off-by: Chun-Tse Shao 
Tested-by: Zide Chen 
Acked-by: Namhyung Kim 
Cc: Adrian Hunter 
Cc: Alexander Shishkin 
Cc: Ian Rogers 
Cc: Ingo Molnar 
Cc: James Clark 
Cc: Jiri Olsa 
Cc: Leo Yan 
Cc: Mark Rutland 
Cc: Peter Zijlstra 
Cc: Sandipan Das 
Cc: Thomas Falcon 
Cc: Yang Li 
Signed-off-by: Arnaldo Carvalho de Melo

perf jevents: Add IOMMU metrics for Intel

2026-05-30T00:12:53+00:00

Add IOMMU Translation Lookaside Buffer (TLB) and interrupt cache metrics
to perf jevents for Intel platforms. This enhances I/O performance
observability, allowing fleet-wide monitoring of IOMMU overhead.

These metrics are supported on platforms that expose the required uncore
IIO IOMMU events (such as Emerald Rapids and Granite Rapids).

The Intel implementation dynamically detects event availability at
generation time.

It requires at least the TLB events to expose the metric group, while
the interrupt cache events are optional. This allows platforms like
Emerald Rapids, which lack IOMMU interrupt cache events, to still expose
the IOMMU TLB metrics.

The following metrics are added:

- iotlb_total_hit: Total IOTLB hits (4K, 2M, 1G pages).
- iotlb_total_miss: Total IOTLB misses.
- iotlb_miss_rate: IOTLB miss rate.
- iotlb_interrupt_cache_hit: Interrupt cache hits.
- iotlb_interrupt_cache_miss: Interrupt cache misses (calculated as
  lookup - hit, clamped to zero).
- iotlb_interrupt_cache_lookup: Interrupt cache lookups.
- iotlb_interrupt_cache_miss_rate: Interrupt cache miss rate.

Tested:
  # perf stat -M \
    iotlb_total_hit,iotlb_total_miss,iotlb_miss_rate \
    --per-socket --metric-only -a -j -- sleep 10
  {"socket" : "S0", "counters" : 10,
   "hits  iotlb_total_hit" : "3579249.0",
   "%  iotlb_miss_rate" : "0.0",
   "misses  iotlb_total_miss" : "3.0"}
  {"socket" : "S1", "counters" : 10,
   "hits  iotlb_total_hit" : "0.0",
   "%  iotlb_miss_rate" : "0.0",
   "misses  iotlb_total_miss" : "0.0"}

Reviewed-by: Ian Rogers 
Signed-off-by: Chun-Tse Shao 
Assisted-by: Gemini:gemini-3.1-pro-preview
Cc: Adrian Hunter 
Cc: Alexander Shishkin 
Cc: Dapeng Mi 
Cc: Ingo Molnar 
Cc: James Clark 
Cc: Jiri Olsa 
Cc: Mark Rutland 
Cc: Namhyung Kim 
Cc: Perry Taylor 
Cc: Peter Zijlstra 
Cc: Sandipan Das 
Link: https://lore.kernel.org/r/20260528234455.434027-3-ctshao@google.com
Signed-off-by: Arnaldo Carvalho de Melo

perf jevents: Add IOMMU metrics for AMD

2026-05-30T00:12:46+00:00

Add IOMMU Translation Lookaside Buffer (TLB) and interrupt cache metrics
to perf jevents for AMD platforms. This enhances I/O performance
observability, allowing fleet-wide monitoring of IOMMU overhead.

These metrics are supported on Zen 2 and newer processors (Rome, Milan,
Genoa, Turin) and are implemented using the standard `amd_iommu` PMU
events. The implementation uses the existing `_zen_model` helper to
ensure these are only generated for Zen 2+. Note that the pde events on
AMD cover both 2M and 1G pages, so 1G pages are implicitly included in
the total hits/misses metrics (sum of pte and pde events).

The following metrics are added:
- iotlb_total_hit: Total IOTLB hits (4K, 2M, 1G pages).
- iotlb_total_miss: Total IOTLB misses.
- iotlb_miss_rate: IOTLB miss rate.
- iotlb_interrupt_cache_hit: Interrupt cache hits.
- iotlb_interrupt_cache_miss: Interrupt cache misses.
- iotlb_interrupt_cache_lookup: Interrupt cache lookups.
- iotlb_interrupt_cache_miss_rate: Interrupt cache miss rate.

Tested:
  # perf stat -M \
    iotlb_total_hit,iotlb_total_miss,iotlb_miss_rate \
    --per-socket --metric-only -a -j -- sleep 10
  {"socket" : "S0", "counters" : 10,
   "hits  iotlb_total_hit" : "3579249.0",
   "%  iotlb_miss_rate" : "0.0",
   "misses  iotlb_total_miss" : "3.0"}
  {"socket" : "S1", "counters" : 10,
   "hits  iotlb_total_hit" : "0.0",
   "%  iotlb_miss_rate" : "0.0",
   "misses  iotlb_total_miss" : "0.0"}

Reviewed-by: Ian Rogers 
Reviewed-by: Sandipan Das 
Signed-off-by: Chun-Tse Shao 
Assisted-by: Gemini:gemini-3.1-pro-preview
Cc: Adrian Hunter 
Cc: Alexander Shishkin 
Cc: Dapeng Mi 
Cc: Ingo Molnar 
Cc: James Clark 
Cc: Jiri Olsa 
Cc: Mark Rutland 
Cc: Namhyung Kim 
Cc: Perry Taylor 
Cc: Peter Zijlstra 
Signed-off-by: Arnaldo Carvalho de Melo

perf vendor events intel: Update sierraforest events from 1.15 to 1.17

2026-05-29T23:56:29+00:00

The updated events and metrics were published in:

  https://github.com/intel/perfmon/commit/efa15280e0577982744642a77af18208aab3635b
  https://github.com/intel/perfmon/commit/5cdba6c2ccfde2ec13e0e701bc2a374849ce9a44

Reviewed-by: Dapeng Mi 
Signed-off-by: Ian Rogers 
Cc: Adrian Hunter 
Cc: Alexander Shishkin 
Cc: Andreas Färber 
Cc: Ingo Molnar 
Cc: James Clark 
Cc: Jiri Olsa 
Cc: Manivannan Sadhasivam 
Cc: Namhyung Kim 
Cc: Peter Zijlstra 
Cc: Thomas Falcon 
Signed-off-by: Arnaldo Carvalho de Melo

perf vendor events intel: Update sapphirerapids events from 1.36 to 1.39

2026-05-29T23:56:05+00:00

The updated events and metrics were published in:

  https://github.com/intel/perfmon/commit/0718b785554ba9bb7f87ad2b838cf25bab5bfa9c
  https://github.com/intel/perfmon/commit/42fe96774f8bda1d67c6ad7ef7f45b27fae7c696

Reviewed-by: Dapeng Mi 
Signed-off-by: Ian Rogers 
Cc: Adrian Hunter 
Cc: Alexander Shishkin 
Cc: Andreas Färber 
Cc: Ingo Molnar 
Cc: James Clark 
Cc: Jiri Olsa 
Cc: Manivannan Sadhasivam 
Cc: Namhyung Kim 
Cc: Peter Zijlstra 
Cc: Thomas Falcon 
Signed-off-by: Arnaldo Carvalho de Melo

perf vendor events intel: Update pantherlake events from 1.04 to 1.05

2026-05-29T23:55:51+00:00

The updated events and metrics were published in:

  https://github.com/intel/perfmon/commit/f5593317a6dee0d11bb2db9a5895db1f231267a9

Reviewed-by: Dapeng Mi 
Signed-off-by: Ian Rogers 
Cc: Adrian Hunter 
Cc: Alexander Shishkin 
Cc: Andreas Färber 
Cc: Ingo Molnar 
Cc: James Clark 
Cc: Jiri Olsa 
Cc: Manivannan Sadhasivam 
Cc: Namhyung Kim 
Cc: Peter Zijlstra 
Cc: Thomas Falcon 
Signed-off-by: Arnaldo Carvalho de Melo

perf vendor events intel: Update meteorlake events from 1.20 to 1.21

2026-05-29T23:55:32+00:00

The updated events and metrics were published in:

  https://github.com/intel/perfmon/commit/419a6600ad2019d4acbf0f79cc54cde85164afc1

Reviewed-by: Dapeng Mi 
Signed-off-by: Ian Rogers 
Cc: Adrian Hunter 
Cc: Alexander Shishkin 
Cc: Andreas Färber 
Cc: Ingo Molnar 
Cc: James Clark 
Cc: Jiri Olsa 
Cc: Manivannan Sadhasivam 
Cc: Namhyung Kim 
Cc: Peter Zijlstra 
Cc: Thomas Falcon 
Signed-off-by: Arnaldo Carvalho de Melo

perf vendor events intel: Update lunarlake events from 1.21 to 1.22

2026-05-29T23:55:18+00:00

The updated events and metrics were published in:

  https://github.com/intel/perfmon/commit/fae822a0f9318e602902eeb2166b966a28c715f8

Reviewed-by: Dapeng Mi 
Signed-off-by: Ian Rogers 
Cc: Adrian Hunter 
Cc: Alexander Shishkin 
Cc: Andreas Färber 
Cc: Ingo Molnar 
Cc: James Clark 
Cc: Jiri Olsa 
Cc: Manivannan Sadhasivam 
Cc: Namhyung Kim 
Cc: Peter Zijlstra 
Cc: Thomas Falcon 
Signed-off-by: Arnaldo Carvalho de Melo