linux-toradex.git/tools/testing/selftests/kvm/include/riscv, branch master

Merge tag 'kvm-riscv-6.20-1' of https://github.com/kvm-riscv/linux into HEAD

2026-02-11T17:45:00+00:00

KVM/riscv changes for 6.20

- Fixes for issues discoverd by KVM API fuzzing in
  kvm_riscv_aia_imsic_has_attr(), kvm_riscv_aia_imsic_rw_attr(),
  and kvm_riscv_vcpu_aia_imsic_update()
- Allow Zalasr, Zilsd and Zclsd extensions for Guest/VM
- Add riscv vm satp modes in KVM selftests
- Transparent huge page support for G-stage
- Adjust the number of available guest irq files based on
  MMIO register sizes in DeviceTree or ACPI

KVM: riscv: selftests: Add riscv vm satp modes

2026-02-06T13:35:23+00:00

Current vm modes cannot represent riscv guest modes precisely, here add
all 9 combinations of P(56,40,41) x V(57,48,39). Also the default vm
mode is detected on runtime instead of hardcoded one, which might not be
supported on specific machine.

Signed-off-by: Wu Fei 
Reviewed-by: Andrew Jones 
Reviewed-by: Nutty Liu 
Reviewed-by: Anup Patel 
Link: https://lore.kernel.org/r/20251105151442.28767-1-wu.fei9@sanechips.com.cn
Signed-off-by: Anup Patel

KVM: selftests: Add a "struct kvm_mmu_arch arch" member to kvm_mmu

2026-01-08T20:02:09+00:00

Add an arch structure+field in "struct kvm_mmu" so that architectures can
track arch-specific information for a given MMU.

No functional change intended.

Reviewed-by: Yosry Ahmed 
Link: https://patch.msgid.link/20251230230150.4150236-9-seanjc@google.com
Signed-off-by: Sean Christopherson

KVM: riscv: selftests: Add missing headers for new testcases

2025-09-16T05:23:55+00:00

Add missing headers to fix the build for new RISC-V KVM selftests.

Signed-off-by: Quan Zhou 
Signed-off-by: Dong Yang 
Reviewed-by: Andrew Jones 
Link: https://lore.kernel.org/r/bfb66541918de68cd89b83bc3430af94bdc75a85.1756710918.git.dayss1224@gmail.com
Signed-off-by: Anup Patel

KVM: riscv: selftests: Decode stval to identify exact exception type

2025-05-21T04:04:37+00:00

Currently, the sbi_pmu_test continues if the exception type is illegal
instruction because access to hpmcounter will generate that. However
illegal instruction exception may occur due to the other reasons
which should result in test assertion.

Use the stval to decode the exact type of instructions and which csrs are
being accessed if it is csr access instructions. Assert in all cases
except if it is a csr access instructions that access valid PMU related
registers.

Take this opportunity to remove the CSR_CYCLEH reference as the test is
compiled for RV64 only.

Reviewed-by: Anup Patel 
Reviewed-by: Andrew Jones 
Signed-off-by: Atish Patra 
Link: https://lore.kernel.org/r/20250430-kvm_selftest_improve-v3-2-eea270ff080b@rivosinc.com
Signed-off-by: Anup Patel

KVM: riscv: selftests: Align the trap information wiht pt_regs

2025-05-21T04:04:35+00:00

The current exeception register structure in selftests are missing
few registers (e.g stval). Instead of adding it manually, change
the ex_regs to align with pt_regs to make it future proof.

Suggested-by: Andrew Jones 
Reviewed-by: Andrew Jones 
Signed-off-by: Atish Patra 
Link: https://lore.kernel.org/r/20250430-kvm_selftest_improve-v3-1-eea270ff080b@rivosinc.com
Signed-off-by: Anup Patel

KVM: riscv: selftests: Add a test for PMU snapshot functionality

2024-04-26T07:44:10+00:00

Verify PMU snapshot functionality by setting up the shared memory
correctly and reading the counter values from the shared memory
instead of the CSR.

Reviewed-by: Andrew Jones 
Reviewed-by: Anup Patel 
Signed-off-by: Atish Patra 
Link: https://lore.kernel.org/r/20240420151741.962500-23-atishp@rivosinc.com
Signed-off-by: Anup Patel

KVM: riscv: selftests: Add SBI PMU extension definitions

2024-04-26T07:44:04+00:00

The SBI PMU extension definition is required for upcoming SBI PMU
selftests.

Reviewed-by: Andrew Jones 
Reviewed-by: Anup Patel 
Signed-off-by: Atish Patra 
Link: https://lore.kernel.org/r/20240420151741.962500-21-atishp@rivosinc.com
Signed-off-by: Anup Patel

KVM: riscv: selftests: Add helper functions for extension checks

2024-04-26T07:44:00+00:00

__vcpu_has_ext can check both SBI and ISA extensions when the first
argument is properly converted to SBI/ISA extension IDs. Introduce
two helper functions to make life easier for developers so they
don't have to worry about the conversions.

Replace the current usages as well with new helpers.

Reviewed-by: Andrew Jones 
Signed-off-by: Atish Patra 
Reviewed-by: Anup Patel 
Link: https://lore.kernel.org/r/20240420151741.962500-19-atishp@rivosinc.com
Signed-off-by: Anup Patel

KVM: riscv: selftests: Move sbi definitions to its own header file

2024-04-26T07:43:57+00:00

The SBI definitions will continue to grow. Move the sbi related
definitions to its own header file from processor.h

Suggested-by: Andrew Jones 
Reviewed-by: Andrew Jones 
Signed-off-by: Atish Patra 
Reviewed-by: Anup Patel 
Link: https://lore.kernel.org/r/20240420151741.962500-18-atishp@rivosinc.com
Signed-off-by: Anup Patel