linux-toradex.git/tools/testing/selftests/resctrl, branch master

selftests/resctrl: Enable dynamic management of IMC counters via linked list

2026-09-26T19:15:26+00:00

Remove the static array and the count and upper limit checks during
initialization, allowing the system to dynamically use all available
IMC counters detected by hardware.

Link: https://lore.kernel.org/r/20260801092429.533956-4-wuyifan50@huawei.com
Reviewed-by: Reinette Chatre 
Signed-off-by: Yifan Wu 
Signed-off-by: Shuah Khan

selftests/resctrl: Replace counter index references with pointers

2026-09-26T19:15:20+00:00

Replace direct counter number references with pointers to remove the
dependency on fixed array indexing and enable the use of different
data structures for counter management.

Link: https://lore.kernel.org/r/20260801092429.533956-3-wuyifan50@huawei.com
Reviewed-by: Reinette Chatre 
Signed-off-by: Yifan Wu 
Signed-off-by: Shuah Khan

selftests/resctrl: Introduce linked list management for IMC counters

2026-09-26T19:15:14+00:00

The static array approach to managing IMC counters has fixed size
constraints and limited compatibility and scalability. Introduce
a linked list-based dynamic management infrastructure to address
these limitations. Add the core data structure definitions and
memory allocation and cleanup functions for dynamic counter
configurations.

Link: https://lore.kernel.org/r/20260801092429.533956-2-wuyifan50@huawei.com
Reviewed-by: Reinette Chatre 
Signed-off-by: Yifan Wu 
Signed-off-by: Shuah Khan

selftests/resctrl: Skip L3_CAT when no exclusive cache portion exists

2026-09-25T20:03:19+00:00

L3_CAT requires an exclusive cache portion to test cache allocation.
This means that the cache portion used by the test can't overlap with
cache portions into which other agents may allocate.

Some platforms legitimately report every cache portion as shareable,
leaving no exclusive cache portion for the test and causing L3_CAT to
fail.

Skip the L3_CAT when the platform has no exclusive cache portion that
the test can use.

Link: https://lore.kernel.org/r/20260821003908.12977-1-icheng@nvidia.com
Tested-by: Chen Yu 
Reviewed-by: Ilpo Järvinen 
Signed-off-by: Richard Cheng 
Reviewed-by: Reinette Chatre 
Signed-off-by: Shuah Khan

selftests/resctrl: Reduce L2 impact on CAT test

2026-05-05T00:40:02+00:00

The L3 CAT test loads a buffer into cache that is proportional to the L3
size allocated for the workload and measures cache misses when accessing
the buffer as a test of L3 occupancy. When loading the buffer it can be
assumed that a portion of the buffer will be loaded into the L2 cache and
depending on cache design may not be present in L3. It is thus possible
for data to not be in L3 but also not trigger an L3 cache miss when
accessed.

Reduce impact of L2 on the L3 CAT test by, if L2 allocation is supported,
minimizing the portion of L2 that the workload can allocate into. This
encourages most of buffer to be loaded into L3 and support better
comparison between buffer size, cache portion, and cache misses when
accessing the buffer.

Link: https://lore.kernel.org/r/1f5aad318889cd6d4f9a8d8b0fbe83e3848d41a9.1775266384.git.reinette.chatre@intel.com
Signed-off-by: Reinette Chatre 
Tested-by: Chen Yu 
Reviewed-by: Ilpo Järvinen 
Signed-off-by: Shuah Khan

selftests/resctrl: Simplify perf usage in CAT test

2026-05-05T00:40:02+00:00

The CAT test relies on the PERF_COUNT_HW_CACHE_MISSES event to determine if
modifying a cache portion size is successful. This event is configured to
report the data as part of an event group, but no other events are added to
the group.

Remove the unnecessary PERF_FORMAT_GROUP format setting. This eliminates
the need for struct perf_event_read and results in read() of the associated
file descriptor to return just one value associated with the
PERF_COUNT_HW_CACHE_MISSES event of interest.

Link: https://lore.kernel.org/r/fb69325eba5031b735fa79effaaacd797c9c6040.1775266384.git.reinette.chatre@intel.com
Signed-off-by: Reinette Chatre 
Tested-by: Chen Yu 
Reviewed-by: Ilpo Järvinen 
Signed-off-by: Shuah Khan

selftests/resctrl: Remove requirement on cache miss rate

2026-05-05T00:40:02+00:00

As the CAT test reads the same buffer into different sized cache portions
it compares the number of cache misses against an expected percentage
based on the size of the cache portion.

Systems and test conditions vary. The CAT test is a test of resctrl
subsystem health and not a test of the hardware architecture so it is not
required to place requirements on the size of the difference in cache
misses, just that the number of cache misses when reading a buffer
increase as the cache portion used for the buffer decreases.

Remove additional constraint on how big the difference between cache
misses should be as the cache portion size changes. Only test that the
cache misses increase as the cache portion size decreases. This remains
a good sanity check of resctrl subsystem health while reducing impact
of hardware architectural differences and the various conditions under
which the test may run.

Increase the size difference between cache portions to additionally avoid
any consequences resulting from smaller increments.

Link: https://lore.kernel.org/r/6de4da5486354c0f25fef0d194956470cb744041.1775266384.git.reinette.chatre@intel.com
Signed-off-by: Reinette Chatre 
Tested-by: Chen Yu 
Reviewed-by: Ilpo Järvinen 
Signed-off-by: Shuah Khan

selftests/resctrl: Raise threshold at which MBM and PMU values are compared

2026-05-05T00:40:02+00:00

Commit 501cfdba0a40 ("selftests/resctrl: Do not compare performance
counters and resctrl at low bandwidth") introduced a threshold under which
memory bandwidth values from MBM and performance counters are not compared.
This is needed because MBM and the PMUs do not have an identical view of
memory bandwidth since PMUs can count all memory traffic while MBM does not
count "overhead" (for example RAS) traffic that cannot be attributed to an
RMID. As a ratio this difference in view of memory bandwidth is pronounced
at low memory bandwidths.

The 750MiB threshold was chosen arbitrarily after comparisons on different
platforms. Exposed to more platforms after introduction this threshold has
proven to be inadequate.

Having accurate comparison between performance counters and MBM requires
careful management of system load as well as control of features that
introduce extra memory traffic, for example, patrol scrub. This is not
appropriate for the resctrl selftests that are intended to run on a
variety of systems with various configurations.

Increase the memory bandwidth threshold under which no comparison is made
between performance counters and MBM. Add additional leniency by increasing
the percentage of difference that will be tolerated between these counts.

There is no impact to the validity of the resctrl selftests results as a
measure of resctrl subsystem health.

Link: https://lore.kernel.org/r/b374c33ddd324130d6255cbb91c3dd500e8277e7.1775266384.git.reinette.chatre@intel.com
Signed-off-by: Reinette Chatre
Tested-by: Chen Yu
Reviewed-by: Ilpo Järvinen
Signed-off-by: Shuah Khan

selftests/resctrl: Increase size of buffer used in MBM and MBA tests

2026-05-05T00:40:02+00:00

Errata for Sierra Forest [1] (SRF42) and Granite Rapids [2] (GNR12)
describe the problem that MBM on Intel RDT may overcount memory bandwidth
measurements. The resctrl tests compare memory bandwidth reported by iMC
PMU to that reported by MBM causing the tests to fail on these systems
depending on the settings of the platform related to the errata.

Since the resctrl tests need to run under various conditions it is not
possible to ensure system settings are such that MBM will not overcount.
It has been observed that the overcounting can be controlled via the
buffer size used in the MBM and MBA tests that rely on comparisons
between iMC PMU and MBM measurements.

Running the MBM test on affected platforms with different buffer sizes it
can be observed that the difference between iMC PMU and MBM counts reduce
as the buffer size increases. After increasing the buffer size to more
than 4X the differences between iMC PMU and MBM become insignificant.

Increase the buffer size used in MBM and MBA tests to 4X L3 size to reduce
possibility of tests failing due to difference in counts reported by iMC
PMU and MBM.

Link: https://lore.kernel.org/r/1bd4d8c5fc791234b0a9da94f29a3e278ba2f7ee.1775266384.git.reinette.chatre@intel.com
Signed-off-by: Reinette Chatre 
Tested-by: Chen Yu 
Reviewed-by: Ilpo Järvinen 
Link: https://edc.intel.com/content/www/us/en/design/products-and-solutions/processors-and-chipsets/sierra-forest/xeon-6700-series-processor-with-e-cores-specification-update/errata-details/ # [1]
Link: https://edc.intel.com/content/www/us/en/design/products-and-solutions/processors-and-chipsets/birch-stream/xeon-6900-6700-6500-series-processors-with-p-cores-specification-update/011US/errata-details/ # [2]
Signed-off-by: Shuah Khan

selftests/resctrl: Support multiple events associated with iMC

2026-05-05T00:40:02+00:00

The resctrl selftests discover needed parameters to perf_event_open() via
sysfs. The PMU associated with every memory controller (iMC) is discovered
via the /sys/bus/event_source/devices/uncore_imc_N/type file while
the read memory bandwidth event type and umask is discovered via
/sys/bus/event_source/devices/uncore_imc_N/events/cas_count_read.

Newer systems may have multiple events that expose read memory bandwidth.
Running a recent kernel that includes
commit 6a8a48644c4b ("perf/x86/intel/uncore: Add per-scheduler IMC CAS count events")
on these systems expose the multiple events. For example,
/sys/bus/event_source/devices/uncore_imc_N/events/cas_count_read_sch0
/sys/bus/event_source/devices/uncore_imc_N/events/cas_count_read_sch1

Support parsing of iMC PMU properties when the PMU may have multiple events
to measure read memory bandwidth. The PMU only needs to be discovered once.
Split the parsing of event details from actual PMU discovery in order to
loop over all events associated with the PMU. Match all events with the
cas_count_read prefix instead of requiring there to be one file with that
name.

Make the parsing code more robust. With strings passed around to create
needed paths, use snprintf() instead of sprintf() to ensure there is
always enough space to create the path while using the standard PATH_MAX
for path lengths. Ensure there is enough room in imc_counters_config[]
before attempting to add an entry.

Link: https://lore.kernel.org/r/b03ca0fa21a09500c56ee589e32516c2c5effeaf.1775266384.git.reinette.chatre@intel.com
Signed-off-by: Reinette Chatre
Tested-by: Chen Yu
Reviewed-by: Zide Chen
Reviewed-by: Ilpo Järvinen
Signed-off-by: Shuah Khan