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| author | Shengjiu Wang <shengjiu.wang@nxp.com> | 2017-11-17 16:29:46 +0800 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 15:48:30 +0800 |
| commit | e71db44eb026adb9502e4fd363cf32b79dd6347d (patch) | |
| tree | 4f3eb1558b255f93dc0f887170ae66e45b4153a9 /.get_maintainer.ignore | |
| parent | 5cfc86a07a661552eef70ec708027c8a39f7e6fa (diff) | |
MLK-16839-1: ASoC: fsl_asrc: selec a proper clock source from the clock list
In internal ratio mode, when the clock rate can't be divided with no
remainder, The final convert ratio is not as expected, there is distortion
in output data.
So need to select a proper clock source for this mode, if can't find a good
clock source, then swith to ideal ratio mode.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Diffstat (limited to '.get_maintainer.ignore')
0 files changed, 0 insertions, 0 deletions