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authorLinus Walleij <linus.walleij@linaro.org>2018-11-27 21:53:58 +0100
committerBoris Brezillon <boris.brezillon@bootlin.com>2018-12-06 16:57:13 +0100
commit9d3b5086f6d42e358f491e5d841750587f3d8cf3 (patch)
treeed1e14a6967610d129c5163d28bb168c397a03b5 /.mailmap
parentb3dd93030c3cdd3f191aa170ccafc2b4d316f4cc (diff)
mtd: physmap_of_gemini: Handle pin control
This enables the complex mapping for the Gemini and kicks in custom read/write functions that will wrap the existing simple functions in calls to enable/disable the parallel flash pins using pin controls. This is necessary on some hardware such as the D-Link DIR-685 where all flash pins are patched in/out at the same time, but some of the flash pins are in practice unused by the flash and have anyway been reused as GPIO. This concerns specifically CE1 on the Gemini. There is only one flash chip, so only CE0 is used, and the line for CE1 has been reused as chip select for the emulated SPI port connected to the display. If we try to use the same lines for flash and GPIO at the same time, one of them will loose: the GPIO line will disappear because it gets disconnected from the pin when the flash group is muxed out. Fix this by introducing two pin control states named simply "enabled" and "disabled" and only enable the flash lines when absolutely necessary (during read/write/copy). This way, they are available for GPIO at all other times and the display works. Collect all the state variables in a struct named struct gemini_flash and allocate this struct at probe time. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
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