i.MX27 Litekit board support

The i.MX27 Litekit is based off of Freescale's i.MX27 processor.  This patch
adds the basic board support files and memory map information for this board.

Signed-off-by: John Scherzer <john.scherzer@timesys.com>
Acked-by: Justin Waters <justin.waters@timesys.com>

5 files changed, 1957 insertions, 0 deletions

diff --git a/arch/arm/mach-mx27/Kconfig b/arch/arm/mach-mx27/Kconfig
index 062dd2940845..2b1e255c09ee 100644
--- a/arch/arm/mach-mx27/Kconfig
+++ b/arch/arm/mach-mx27/Kconfig
@@ -1,6 +1,13 @@
 menu "MX27 Options"
 	depends on ARCH_MX27
 
+config MACH_MX27LITE
+	bool "Support MX27LITE platforms"
+	default y
+	help
+	  Include support for MX27LITE platform. This includes specific
+	  configurations for the board and its peripherals.
+
 config MACH_MX27ADS
 	bool "Support MX27ADS platforms"
 	default y
diff --git a/arch/arm/mach-mx27/Makefile b/arch/arm/mach-mx27/Makefile
index 56322326e7e0..ecafd4091bbe 100644
--- a/arch/arm/mach-mx27/Makefile
+++ b/arch/arm/mach-mx27/Makefile
@@ -6,6 +6,7 @@
 
 obj-y := mm.o time.o dma.o gpio_mux.o clock.o devices.o serial.o system.o usb.o cpu.o
 obj-$(CONFIG_MACH_MX27ADS)	+= mx27ads.o mx27ads_gpio.o
+obj-$(CONFIG_MACH_MX27LITE)	+= mx27lite.o mx27lite_gpio.o
 
 # power management
 obj-$(CONFIG_PM) 		+= pm.o mxc_pm.o
diff --git a/arch/arm/mach-mx27/mx27lite.c b/arch/arm/mach-mx27/mx27lite.c
new file mode 100644
index 000000000000..bdd480a76dab
--- /dev/null
+++ b/arch/arm/mach-mx27/mx27lite.c
@@ -0,0 +1,754 @@
+/*
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd
+ *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
+ *  Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/types.h>
+#include <linux/sched.h>
+#include <linux/interrupt.h>
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <linux/device.h>
+#include <linux/input.h>
+#include <linux/nodemask.h>
+#include <linux/clk.h>
+#include <linux/spi/spi.h>
+#include <linux/serial_8250.h>
+#if defined(CONFIG_MTD) || defined(CONFIG_MTD_MODULE)
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/map.h>
+#include <linux/mtd/partitions.h>
+
+#include <asm/mach/flash.h>
+#endif
+
+#include <asm/hardware.h>
+#include <asm/irq.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/irq.h>
+#include <asm/arch/memory.h>
+#include <asm/arch/gpio.h>
+#include <asm/mach/keypad.h>
+#include "gpio_mux.h"
+#include "board-mx27ads.h"
+
+/*!
+ * @file mach-mx27/mx27ads.c
+ * @brief This file contains the board specific initialization routines.
+ *
+ * @ingroup MSL_MX27
+ */
+
+extern void mxc_map_io(void);
+extern void mxc_init_irq(void);
+extern void mxc_cpu_init(void) __init;
+extern void mxc_clocks_init(void);
+extern void mxc_cpu_common_init(void);
+extern struct sys_timer mxc_timer;
+extern void __init early_console_setup(char *);
+
+static char command_line[COMMAND_LINE_SIZE];
+static int mxc_card_status;
+int mxc_board_is_ads = 1;
+
+static void mxc_nop_release(struct device *dev)
+{
+	/* Nothing */
+}
+
+unsigned long board_get_ckih_rate(void)
+{
+	return 26000000;
+}
+
+#if defined(CONFIG_CS89x0) || defined(CONFIG_CS89x0_MODULE)
+/*! Null terminated portlist used to probe for the CS8900A device on ISA Bus
+ * Add 3 to reset the page window before probing (fixes eth probe when deployed
+ * using nand_boot)
+ */
+unsigned int netcard_portlist[] = { CS8900A_BASE_ADDRESS + 3, 0 };
+
+EXPORT_SYMBOL(netcard_portlist);
+/*!
+ * The CS8900A has 4 IRQ pins, which is software selectable, CS8900A interrupt
+ * pin 0 is used for interrupt generation.
+ */
+unsigned int cs8900_irq_map[] = { CS8900AIRQ, 0, 0, 0 };
+
+EXPORT_SYMBOL(cs8900_irq_map);
+#endif
+
+#if defined(CONFIG_FEC) || defined(CONFIG_FEC_MODULE)
+unsigned int expio_intr_fec = MXC_EXP_IO_BASE + 7;
+
+EXPORT_SYMBOL(expio_intr_fec);
+#endif
+
+#if defined(CONFIG_KEYBOARD_MXC) || defined(CONFIG_KEYBOARD_MXC_MODULE)
+
+/*!
+ * This array is used for mapping mx27 ADS keypad scancodes to input keyboard
+ * keycodes.
+ */
+static u16 mxckpd_keycodes[] = {
+	KEY_KP9, KEY_LEFTSHIFT, KEY_0, KEY_KPASTERISK, KEY_RECORD, KEY_POWER,
+	KEY_KP8, KEY_9, KEY_8, KEY_7, KEY_KP5, KEY_VOLUMEDOWN,
+	KEY_KP7, KEY_6, KEY_5, KEY_4, KEY_KP4, KEY_VOLUMEUP,
+	KEY_KP6, KEY_3, KEY_2, KEY_1, KEY_KP3, KEY_DOWN,
+	KEY_BACK, KEY_RIGHT, KEY_ENTER, KEY_LEFT, KEY_HOME, KEY_KP2,
+	KEY_END, KEY_F2, KEY_UP, KEY_F1, KEY_F4, KEY_KP1,
+};
+
+static struct keypad_data evb_6_by_6_keypad = {
+	.rowmax = 6,
+	.colmax = 6,
+	.irq = INT_KPP,
+	.learning = 0,
+	.delay = 2,
+	.matrix = mxckpd_keycodes,
+};
+
+static struct resource mxc_kpp_resources[] = {
+	[0] = {
+	       .start = INT_KPP,
+	       .end = INT_KPP,
+	       .flags = IORESOURCE_IRQ,
+	       }
+};
+
+/* mxc keypad driver */
+static struct platform_device mxc_keypad_device = {
+	.name = "mxc_keypad",
+	.id = 0,
+	.num_resources = ARRAY_SIZE(mxc_kpp_resources),
+	.resource = mxc_kpp_resources,
+	.dev = {
+		.release = mxc_nop_release,
+		.platform_data = &evb_6_by_6_keypad,
+		},
+};
+
+static void mxc_init_keypad(void)
+{
+	(void)platform_device_register(&mxc_keypad_device);
+}
+#else
+static inline void mxc_init_keypad(void)
+{
+}
+#endif
+
+/* MTD NOR flash */
+
+#if defined(CONFIG_MTD_MXC) || defined(CONFIG_MTD_MXC_MODULE)
+
+static struct mtd_partition mxc_nor_partitions[] = {
+	{
+	 .name = "Bootloader",
+	 .size = 512 * 1024,
+	 .offset = 0x00000000,
+	 .mask_flags = MTD_WRITEABLE	/* force read-only */
+	 },
+	{
+	 .name = "nor.Kernel",
+	 .size = 2 * 1024 * 1024,
+	 .offset = MTDPART_OFS_APPEND,
+	 .mask_flags = 0},
+	{
+	 .name = "nor.userfs",
+	 .size = 14 * 1024 * 1024,
+	 .offset = MTDPART_OFS_APPEND,
+	 .mask_flags = 0},
+	{
+	 .name = "nor.rootfs",
+	 .size = 12 * 1024 * 1024,
+	 .offset = MTDPART_OFS_APPEND,
+	 .mask_flags = MTD_WRITEABLE},
+	{
+	 .name = "FIS directory",
+	 .size = 12 * 1024,
+	 .offset = 0x01FE0000,
+	 .mask_flags = MTD_WRITEABLE	/* force read-only */
+	 },
+	{
+	 .name = "Redboot config",
+	 .size = MTDPART_SIZ_FULL,
+	 .offset = 0x01FFF000,
+	 .mask_flags = MTD_WRITEABLE	/* force read-only */
+	 },
+};
+
+static struct flash_platform_data mxc_flash_data = {
+	.map_name = "cfi_probe",
+	.width = 2,
+	.parts = mxc_nor_partitions,
+	.nr_parts = ARRAY_SIZE(mxc_nor_partitions),
+};
+
+static struct resource mxc_flash_resource = {
+	.start = 0xc0000000,
+	.end = 0xc0000000 + 0x02000000 - 1,
+	.flags = IORESOURCE_MEM,
+
+};
+
+static struct platform_device mxc_nor_mtd_device = {
+	.name = "mxc_nor_flash",
+	.id = 0,
+	.dev = {
+		.release = mxc_nop_release,
+		.platform_data = &mxc_flash_data,
+		},
+	.num_resources = 1,
+	.resource = &mxc_flash_resource,
+};
+
+static void mxc_init_nor_mtd(void)
+{
+	(void)platform_device_register(&mxc_nor_mtd_device);
+}
+#else
+static void mxc_init_nor_mtd(void)
+{
+}
+#endif
+
+/* MTD NAND flash */
+
+#if defined(CONFIG_MTD_NAND_MXC) || defined(CONFIG_MTD_NAND_MXC_MODULE)
+
+static struct mtd_partition mxc_nand_partitions[4] = {
+	{
+	 .name = "IPL-SPL",
+	 .offset = 0,
+	 .size = 128 * 1024},
+	{
+	 .name = "nand.kernel",
+	 .offset = MTDPART_OFS_APPEND,
+	 .size = 4 * 1024 * 1024},
+	{
+	 .name = "nand.rootfs",
+	 .offset = MTDPART_OFS_APPEND,
+	 .size = 22 * 1024 * 1024},
+	{
+	 .name = "nand.userfs",
+	 .offset = MTDPART_OFS_APPEND,
+	 .size = MTDPART_SIZ_FULL},
+};
+
+static struct flash_platform_data mxc_nand_data = {
+	.parts = mxc_nand_partitions,
+	.nr_parts = ARRAY_SIZE(mxc_nand_partitions),
+	.width = 1,
+};
+
+static struct platform_device mxc_nand_mtd_device = {
+	.name = "mxc_nand_flash",
+	.id = 0,
+	.dev = {
+		.release = mxc_nop_release,
+		.platform_data = &mxc_nand_data,
+		},
+};
+
+static void mxc_init_nand_mtd(void)
+{
+	(void)platform_device_register(&mxc_nand_mtd_device);
+}
+#else
+static inline void mxc_init_nand_mtd(void)
+{
+}
+#endif
+
+#if defined(CONFIG_FB_MXC_SYNC_PANEL) || defined(CONFIG_FB_MXC_SYNC_PANEL_MODULE)
+static const char fb_default_mode[] = "Sharp-QVGA";
+
+/* mxc lcd driver */
+static struct platform_device mxc_fb_device = {
+	.name = "mxc_sdc_fb",
+	.id = 0,
+	.dev = {
+		.release = mxc_nop_release,
+		.platform_data = &fb_default_mode,
+		.coherent_dma_mask = 0xFFFFFFFF,
+		},
+};
+
+static void mxc_init_fb(void)
+{
+	(void)platform_device_register(&mxc_fb_device);
+}
+#else
+static inline void mxc_init_fb(void)
+{
+}
+#endif
+
+static struct spi_board_info mxc_spi_board_info[] __initdata = {
+	{
+	 .modalias = "pmic_spi",
+	 .irq = IOMUX_TO_IRQ(MX27_PIN_TOUT),
+	 .max_speed_hz = 4000000,
+	 .bus_num = 1,
+	 .chip_select = 0,
+	 },
+};
+
+#if 0
+#define MXC_CARD_DEBUG
+#endif
+
+static const int pbc_card_bit[4][3] = {
+	/* BSTAT            IMR enable       IMR removal */
+	{PBC_BSTAT_SD2_DET, PBC_INTR_SD2_EN, PBC_INTR_SD2_R_EN},
+	{PBC_BSTAT_SD3_DET, PBC_INTR_SD3_EN, PBC_INTR_SD3_R_EN},
+	{PBC_BSTAT_MS_DET, PBC_INTR_MS_EN, PBC_INTR_MS_R_EN},
+	{PBC_BSTAT_SD1_DET, PBC_INTR_SD1_EN, PBC_INTR_SD1_R_EN},
+};
+
+/*!
+ * Check if a SD card has been inserted or not.
+ *
+ * @param  num		a card number as defined in \b enum \b mxc_card_no
+ * @return 0 if a card is not present; non-zero otherwise.
+ */
+int mxc_card_detected(enum mxc_card_no num)
+{
+	u32 status;
+
+	status = __raw_readw(PBC_BSTAT1_REG);
+	return ((status & MXC_BSTAT_BIT(num)) == 0);
+}
+
+/*
+ * Check if there is any state change by reading the IMR register and the
+ * previous and current states of the board status register (offset 0x28).
+ * A state change is defined to be card insertion OR removal. So the driver
+ * may have to call the mxc_card_detected() function to see if it is card
+ * insertion or removal.
+ *
+ * @param  mask		current IMR value
+ * @param  s0		previous status register value (offset 0x28)
+ * @param  s1		current status register value (offset 0x28)
+ *
+ * @return 0 if no card status change OR the corresponding bits in the IMR
+ *           (passed in as 'mask') is NOT set.
+ *         A non-zero value indicates some card state changes. For example,
+ *         0b0001 means SD3 has a card state change (bit0 is set) AND its
+ *               associated insertion or removal bits in IMR is SET.
+ *         0b0100 means SD1 has a card state change (bit2 is set) AND its
+ *               associated insertion or removal bits in IMR is SET.
+ *         0b1001 means both MS and SD3 have state changes
+ */
+static u32 mxc_card_state_changed(u32 mask, u32 s0, u32 s1)
+{
+	u32 i, retval = 0;
+	u32 stat = (s0 ^ s1) & 0x7800;
+
+	if (stat == 0)
+		return 0;
+
+	for (i = MXC_CARD_MIN; i <= MXC_CARD_MAX; i++) {
+		if ((stat & pbc_card_bit[i][0]) != 0 &&
+		    (mask & (pbc_card_bit[i][1] | pbc_card_bit[i][2])) != 0) {
+			retval |= 1 << i;
+		}
+	}
+#ifdef MXC_CARD_DEBUG
+	printk(KERN_INFO "\nmask=%x, s0=%x, s1=%x\n", mask, s0, s1);
+	printk(KERN_INFO "retval=%x, stat=%x\n", retval, stat);
+#endif
+	return retval;
+}
+
+/*!
+ * Interrupt handler for the expio (CPLD) to deal with interrupts from
+ * FEC, external UART, CS8900 Ethernet and SD cards, etc.
+ */
+static void mxc_expio_irq_handler(u32 irq, struct irq_desc *desc)
+{
+	u32 imr, card_int, i;
+	u32 int_valid;
+	u32 expio_irq;
+	u32 stat = __raw_readw(PBC_BSTAT1_REG);
+
+	desc->chip->mask(irq);	/* irq = gpio irq number */
+
+	imr = __raw_readw(PBC_INTMASK_SET_REG);
+
+	card_int = mxc_card_state_changed(imr, mxc_card_status, stat);
+	mxc_card_status = stat;
+
+	if (card_int != 0) {
+		for (i = MXC_CARD_MIN; i <= MXC_CARD_MAX; i++) {
+			if ((card_int & (1 << i)) != 0) {
+				pr_debug("card no %d state changed\n", i);
+			}
+		}
+	}
+
+	/* Bits defined in PBC_INTSTATUS_REG at 0x2C */
+	int_valid = __raw_readw(PBC_INTSTATUS_REG) & imr;
+	/*  combined with the card interrupt valid information */
+	int_valid = (int_valid & 0x0F8E) | (card_int << PBC_INTR_SD2_EN_BIT);
+
+	if (unlikely(!int_valid)) {
+		pr_debug("\nEXPIO: Spurious interrupt:0x%0x\n\n", int_valid);
+		pr_debug("CPLD IMR(0x38)=0x%x, BSTAT1(0x28)=0x%x\n", imr, stat);
+		goto out;
+	}
+
+	expio_irq = MXC_EXP_IO_BASE;
+	for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
+		struct irq_desc *d;
+		if ((int_valid & 1) == 0)
+			continue;
+		d = irq_desc + expio_irq;
+		if (unlikely(!(d->handle_irq))) {
+			printk(KERN_ERR "\nEXPIO irq: %d unhandeled\n",
+			       expio_irq);
+			BUG();	/* oops */
+		}
+		d->handle_irq(expio_irq, d);
+	}
+
+      out:
+	desc->chip->ack(irq);
+	desc->chip->unmask(irq);
+}
+
+#ifdef MXC_CARD_DEBUG
+
+static irqreturn_t mxc_sd_test_handler(int irq, void *desc)
+{
+	int s = -1;
+
+	printk(KERN_INFO "%s(irq=%d) for ", __FUNCTION__, irq);
+	if (irq == EXPIO_INT_SD1_EN) {
+		printk(KERN_INFO "SD1");
+		s = MXC_CARD_SD1;
+	} else if (irq == EXPIO_INT_SD2_EN) {
+		printk(KERN_INFO "SD2");
+		s = MXC_CARD_SD2;
+	} else if (irq == EXPIO_INT_SD3_EN) {
+		printk(KERN_INFO "SD3");
+		s = MXC_CARD_SD3;
+	} else if (irq == EXPIO_INT_MS_EN) {
+		printk(KERN_INFO "MS");
+		s = MXC_CARD_MS;
+	} else {
+		printk(KERN_INFO "None!!!!");
+	}
+	if (mxc_card_detected(s)) {
+		printk(KERN_INFO " inserted\n");
+	} else {
+		printk(KERN_INFO " removed\n");
+	}
+
+	return IRQ_HANDLED;
+}
+#endif				/* MXC_CARD_DEBUG */
+
+/*
+ * Disable an expio pin's interrupt by setting the bit in the imr.
+ * @param irq		an expio virtual irq number
+ */
+static void expio_mask_irq(u32 irq)
+{
+	u32 expio = MXC_IRQ_TO_EXPIO(irq);
+
+	/* mask the interrupt */
+	if (irq < EXPIO_INT_SD2_EN) {
+		__raw_writew(1 << expio, PBC_INTMASK_CLEAR_REG);
+	} else {
+		irq -= EXPIO_INT_SD2_EN;
+		/* clear both SDx_EN and SDx_R_EN bits */
+		__raw_writew((pbc_card_bit[irq][1] | pbc_card_bit[irq][2]),
+			     PBC_INTMASK_CLEAR_REG);
+	}
+}
+
+/*
+ * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr.
+ * @param irq		an expanded io virtual irq number
+ */
+static void expio_ack_irq(u32 irq)
+{
+	u32 expio = MXC_IRQ_TO_EXPIO(irq);
+	/* clear the interrupt status */
+	__raw_writew(1 << expio, PBC_INTSTATUS_REG);
+	/* mask the interrupt */
+	expio_mask_irq(irq);
+}
+
+/*
+ * Enable a expio pin's interrupt by clearing the bit in the imr.
+ * @param irq		an expio virtual irq number
+ */
+static void expio_unmask_irq(u32 irq)
+{
+	u32 expio = MXC_IRQ_TO_EXPIO(irq);
+
+	/* unmask the interrupt */
+	if (irq < EXPIO_INT_SD2_EN) {
+		if (irq == EXPIO_INT_XUART_INTA) {
+			/* Set 8250 MCR register bit 3 - Forces the INT (A-B
+			 * outputs to the active mode and sets OP2 to logic 0.
+			 * This is needed to avoid spurious int caused by the
+			 * internal CPLD pull-up for the interrupt pin.
+			 */
+			u16 val = __raw_readw(MXC_LL_EXTUART_VADDR + 8);
+			__raw_writew(val | 0x8, MXC_LL_EXTUART_VADDR + 8);
+		}
+		__raw_writew(1 << expio, PBC_INTMASK_SET_REG);
+	} else {
+		irq -= EXPIO_INT_SD2_EN;
+
+		if (mxc_card_detected(irq)) {
+			__raw_writew(pbc_card_bit[irq][2], PBC_INTMASK_SET_REG);
+		} else {
+			__raw_writew(pbc_card_bit[irq][1], PBC_INTMASK_SET_REG);
+		}
+	}
+}
+
+static struct irq_chip expio_irq_chip = {
+	.ack = expio_ack_irq,
+	.mask = expio_mask_irq,
+	.unmask = expio_unmask_irq,
+};
+
+static int __init mxc_expio_init(void)
+{
+	int i, ver;
+
+	ver = (__raw_readw(PBC_VERSION_REG) >> 8) & 0xFF;
+	if ((ver & 0x80) != 0) {
+		pr_info("MX27 ADS EXPIO(CPLD) hardware\n");
+		pr_info("CPLD version: 0x%x\n", ver);
+	} else {
+		mxc_board_is_ads = 0;
+		ver &= 0x0F;
+		pr_info("MX27 EVB EXPIO(CPLD) hardware\n");
+		if (ver == 0xF || ver <= MXC_CPLD_VER_1_50)
+			pr_info("Wrong CPLD version: %d\n", ver);
+		else {
+			pr_info("CPLD version: %d\n", ver);
+		}
+	}
+
+	mxc_card_status = __raw_readw(PBC_BSTAT1_REG);
+
+#ifdef MXC_CARD_DEBUG
+	for (i = MXC_CARD_MIN; i <= MXC_CARD_MAX; i++) {
+		if (mxc_card_detected(i)) {
+			pr_info("Card %d is detected\n", 3 - i);
+		}
+	}
+#endif
+	/*
+	 * Configure INT line as GPIO input
+	 */
+	gpio_config_mux(MX27_PIN_TIN, GPIO_MUX_GPIO);
+	mxc_set_gpio_direction(MX27_PIN_TIN, 1);
+
+	/* disable the interrupt and clear the status */
+	__raw_writew(0xFFFF, PBC_INTMASK_CLEAR_REG);
+	__raw_writew(0xFFFF, PBC_INTSTATUS_REG);
+
+	for (i = MXC_EXP_IO_BASE; i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES);
+	     i++) {
+		set_irq_chip(i, &expio_irq_chip);
+		set_irq_handler(i, handle_level_irq);
+		set_irq_flags(i, IRQF_VALID);
+	}
+	set_irq_type(EXPIO_PARENT_INT, IRQT_HIGH);
+	set_irq_chained_handler(EXPIO_PARENT_INT, mxc_expio_irq_handler);
+
+	return 0;
+}
+
+#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
+
+/*!
+ * The serial port definition structure. The fields contain:
+ * {UART, CLK, PORT, IRQ, FLAGS}
+ */
+static struct plat_serial8250_port serial_platform_data[] = {
+	{
+	 .membase = (void __iomem *)(CS4_BASE_ADDR_VIRT + 0x20000),
+	 .mapbase = (unsigned long)(CS4_BASE_ADDR + 0x20000),
+	 .irq = EXPIO_INT_XUART_INTA,
+	 .uartclk = 3686400,
+	 .regshift = 1,
+	 .iotype = UPIO_MEM,
+	 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ,
+	 /*.pm = serial_platform_pm, */
+	 },
+	{},
+};
+
+/*!
+ * REVISIT: document me
+ */
+static struct platform_device serial_device = {
+	.name = "serial8250",
+	.id = 0,
+	.dev = {
+		.platform_data = &serial_platform_data[0],
+		},
+};
+
+/*!
+ * REVISIT: document me
+ */
+static int __init mxc_init_extuart(void)
+{
+	int value;
+	/*reset ext uart in cpld */
+	__raw_writew(PBC_BCTRL1_URST, PBC_BCTRL1_SET_REG);
+	/*delay some time for reset finish */
+	for (value = 0; value < 1000; value++) ;
+	__raw_writew(PBC_BCTRL1_URST, PBC_BCTRL1_CLEAR_REG);
+	return platform_device_register(&serial_device);
+}
+#else
+static inline int mxc_init_extuart(void)
+{
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_MXC_PMIC_MC13783) && defined(CONFIG_SND_MXC_PMIC)
+extern void gpio_ssi_active(int ssi_num);
+
+static void __init mxc_init_pmic_audio(void)
+{
+	struct clk *ssi_clk;
+	struct clk *ckih_clk;
+	struct clk *cko_clk;
+
+	/* Enable 26 mhz clock on CKO1 for PMIC audio */
+	ckih_clk = clk_get(NULL, "ckih");
+	cko_clk = clk_get(NULL, "clko_clk");
+	if (IS_ERR(ckih_clk) || IS_ERR(cko_clk)) {
+		printk(KERN_ERR "Unable to set CLKO output to CKIH\n");
+	} else {
+		clk_set_parent(cko_clk, ckih_clk);
+		clk_set_rate(cko_clk, clk_get_rate(ckih_clk));
+		clk_enable(cko_clk);
+	}
+	clk_put(ckih_clk);
+	clk_put(cko_clk);
+
+	ssi_clk = clk_get(NULL, "ssi_clk.0");
+	clk_enable(ssi_clk);
+	clk_put(ssi_clk);
+	ssi_clk = clk_get(NULL, "ssi_clk.1");
+	clk_enable(ssi_clk);
+	clk_put(ssi_clk);
+
+	gpio_ssi_active(0);
+	gpio_ssi_active(1);
+}
+#else
+static void __inline mxc_init_pmic_audio(void)
+{
+}
+#endif
+
+static __init void mxc_board_init(void)
+{
+	pr_info("AIPI VA base: 0x%x\n", IO_ADDRESS(AIPI_BASE_ADDR));
+	mxc_cpu_common_init();
+	mxc_clocks_init();
+	early_console_setup(saved_command_line);
+	mxc_gpio_init();
+	//mxc_expio_init();
+	mxc_init_keypad();
+	mxc_init_nor_mtd();
+	mxc_init_nand_mtd();
+	mxc_init_extuart();
+	mxc_init_pmic_audio();
+#ifdef MXC_CARD_DEBUG
+	request_irq(EXPIO_INT_SD1_EN, mxc_sd_test_handler, 0, "SD_card1", NULL);
+	request_irq(EXPIO_INT_SD2_EN, mxc_sd_test_handler, 0, "SD_card2", NULL);
+	request_irq(EXPIO_INT_SD3_EN, mxc_sd_test_handler, 0, "SD_card3", NULL);
+	request_irq(EXPIO_INT_MS_EN, mxc_sd_test_handler, 0, "MS_card", NULL);
+#endif
+
+	spi_register_board_info(mxc_spi_board_info,
+				ARRAY_SIZE(mxc_spi_board_info));
+
+	mxc_init_fb();
+}
+
+static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags,
+				   char **cmdline, struct meminfo *mi)
+{
+#ifdef CONFIG_KGDB_8250
+	int i;
+	for (i = 0;
+	     i <
+	     (sizeof(serial_platform_data) / sizeof(serial_platform_data[0]));
+	     i += 1)
+		kgdb8250_add_platform_port(i, &serial_platform_data[i]);
+#endif
+
+	mxc_cpu_init();
+	/* Store command line for use on mxc_board_init */
+	strcpy(command_line, *cmdline);
+
+#ifdef CONFIG_DISCONTIGMEM
+	do {
+		int nid;
+		mi->nr_banks = MXC_NUMNODES;
+		for (nid = 0; nid < mi->nr_banks; nid++) {
+			SET_NODE(mi, nid);
+		}
+	} while (0);
+#endif
+}
+
+EXPORT_SYMBOL(mxc_card_detected);
+EXPORT_SYMBOL(mxc_board_is_ads);
+
+/*
+ * The following uses standard kernel macros define in arch.h in order to
+ * initialize __mach_desc_MX27ADS data structure.
+ */
+/* *INDENT-OFF* */
+MACHINE_START(IMX27LITE, "Freescale i.MX27ADS")
+	/* maintainer: Freescale Semiconductor, Inc. */
+#ifdef CONFIG_SERIAL_8250_CONSOLE
+	.phys_io        = CS4_BASE_ADDR,
+	.io_pg_offst    = ((CS4_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+#else
+	.phys_io        = AIPI_BASE_ADDR,
+	.io_pg_offst    = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+#endif
+	.boot_params    = PHYS_OFFSET + 0x100,
+	.fixup          = fixup_mxc_board,
+	.map_io         = mxc_map_io,
+	.init_irq       = mxc_init_irq,
+	.init_machine   = mxc_board_init,
+	.timer          = &mxc_timer,
+MACHINE_END
diff --git a/arch/arm/mach-mx27/mx27lite_gpio.c b/arch/arm/mach-mx27/mx27lite_gpio.c
new file mode 100644
index 000000000000..45b1e68fb791
--- /dev/null
+++ b/arch/arm/mach-mx27/mx27lite_gpio.c
@@ -0,0 +1,1191 @@
+/*
+ *  Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/errno.h>
+#include <linux/module.h>
+#include <linux/device.h>
+#include <asm/io.h>
+#include <asm/hardware.h>
+#include <asm/arch/gpio.h>
+
+#include "board-mx27ads.h"
+#include "gpio_mux.h"
+#include "crm_regs.h"
+
+static int g_uart_activated[MXC_UART_NR] = { 0, 0, 0, 0, 0, 0 };
+
+/*!
+ * @file mach-mx27/mx27ads_gpio.c
+ *
+ * @brief This file contains all the GPIO setup functions for the board.
+ *
+ * @ingroup GPIO_MX27
+ */
+
+/*!
+ * Setup GPIO for a UART port to be active
+ *
+ * @param  port         a UART port
+ * @param  ir_mode      indicates if the port is used for SIR
+ */
+void gpio_uart_active(int port, int ir_mode)
+{
+	if (port < 0 || port >= MXC_UART_NR) {
+		pr_info("Wrong port number: %d\n", port);
+		BUG();
+	}
+
+	if (g_uart_activated[port]) {
+		pr_info("UART %d has been activated multiple times\n", port + 1);
+		return;
+	}
+	g_uart_activated[port] = 1;
+
+	switch (port) {
+	case 0:
+		gpio_request_mux(MX27_PIN_UART1_TXD, GPIO_MUX_PRIMARY);
+		gpio_request_mux(MX27_PIN_UART1_RXD, GPIO_MUX_PRIMARY);
+		gpio_request_mux(MX27_PIN_UART1_CTS, GPIO_MUX_PRIMARY);
+		gpio_request_mux(MX27_PIN_UART1_RTS, GPIO_MUX_PRIMARY);
+		break;
+	case 1:
+		gpio_request_mux(MX27_PIN_UART2_TXD, GPIO_MUX_PRIMARY);
+		gpio_request_mux(MX27_PIN_UART2_RXD, GPIO_MUX_PRIMARY);
+		gpio_request_mux(MX27_PIN_UART2_CTS, GPIO_MUX_PRIMARY);
+		gpio_request_mux(MX27_PIN_UART2_RTS, GPIO_MUX_PRIMARY);
+		break;
+	case 2:
+		gpio_request_mux(MX27_PIN_UART3_TXD, GPIO_MUX_PRIMARY);
+		gpio_request_mux(MX27_PIN_UART3_RXD, GPIO_MUX_PRIMARY);
+		gpio_request_mux(MX27_PIN_UART3_CTS, GPIO_MUX_PRIMARY);
+		gpio_request_mux(MX27_PIN_UART3_RTS, GPIO_MUX_PRIMARY);
+
+		/* enable or disable the IrDA transceiver based on ir_mode */
+		//if (ir_mode == IRDA)
+		//	__raw_writew(PBC_BCTRL2_IRDA_EN, PBC_BCTRL2_CLEAR_REG);
+		//else
+		//	__raw_writew(PBC_BCTRL2_IRDA_EN, PBC_BCTRL2_SET_REG);
+		//break;
+	case 3:
+		gpio_request_mux(MX27_PIN_USBH1_TXDM, GPIO_MUX_ALT);
+		gpio_request_mux(MX27_PIN_USBH1_RXDP, GPIO_MUX_ALT);
+		gpio_request_mux(MX27_PIN_USBH1_TXDP, GPIO_MUX_ALT);
+		gpio_request_mux(MX27_PIN_USBH1_FS, GPIO_MUX_ALT);
+		break;
+	case 4:
+		gpio_request_mux(MX27_PIN_CSI_D6, GPIO_MUX_ALT);
+		gpio_request_mux(MX27_PIN_CSI_D7, GPIO_MUX_ALT);
+		gpio_request_mux(MX27_PIN_CSI_VSYNC, GPIO_MUX_ALT);
+		gpio_request_mux(MX27_PIN_CSI_HSYNC, GPIO_MUX_ALT);
+		break;
+	case 5:
+		gpio_request_mux(MX27_PIN_CSI_D0, GPIO_MUX_ALT);
+		gpio_request_mux(MX27_PIN_CSI_D1, GPIO_MUX_ALT);
+		gpio_request_mux(MX27_PIN_CSI_D2, GPIO_MUX_ALT);
+		gpio_request_mux(MX27_PIN_CSI_D3, GPIO_MUX_ALT);
+		break;
+	default:
+		break;
+	}
+}
+
+/*!
+ * Setup GPIO for a UART port to be inactive
+ *
+ * @param  port         a UART port
+ * @param  ir_mode      indicates if the port is used for SIR
+ */
+void gpio_uart_inactive(int port, int ir_mode)
+{
+	if (port < 0 || port >= MXC_UART_NR) {
+		pr_info("Wrong port number: %d\n", port);
+		BUG();
+	}
+
+	if (g_uart_activated[port] == 0) {
+		pr_info("UART %d has not been activated \n", port + 1);
+		return;
+	}
+	g_uart_activated[port] = 0;
+
+	switch (port) {
+	case 0:
+		gpio_free_mux(MX27_PIN_UART1_TXD);
+		gpio_free_mux(MX27_PIN_UART1_RXD);
+		gpio_free_mux(MX27_PIN_UART1_CTS);
+		gpio_free_mux(MX27_PIN_UART1_RTS);
+		break;
+	case 1:
+		gpio_free_mux(MX27_PIN_UART2_TXD);
+		gpio_free_mux(MX27_PIN_UART2_RXD);
+		gpio_free_mux(MX27_PIN_UART2_CTS);
+		gpio_free_mux(MX27_PIN_UART2_RTS);
+		break;
+	case 2:
+		gpio_free_mux(MX27_PIN_UART3_TXD);
+		gpio_free_mux(MX27_PIN_UART3_RXD);
+		gpio_free_mux(MX27_PIN_UART3_CTS);
+		gpio_free_mux(MX27_PIN_UART3_RTS);
+		break;
+	case 3:
+		gpio_free_mux(MX27_PIN_USBH1_TXDM);
+		gpio_free_mux(MX27_PIN_USBH1_RXDP);
+		gpio_free_mux(MX27_PIN_USBH1_TXDP);
+		gpio_free_mux(MX27_PIN_USBH1_FS);
+		break;
+	case 4:
+		gpio_free_mux(MX27_PIN_CSI_D6);
+		gpio_free_mux(MX27_PIN_CSI_D7);
+		gpio_free_mux(MX27_PIN_CSI_VSYNC);
+		gpio_free_mux(MX27_PIN_CSI_HSYNC);
+		break;
+	case 5:
+		gpio_free_mux(MX27_PIN_CSI_D0);
+		gpio_free_mux(MX27_PIN_CSI_D1);
+		gpio_free_mux(MX27_PIN_CSI_D2);
+		gpio_free_mux(MX27_PIN_CSI_D3);
+		break;
+	default:
+		break;
+	}
+}
+
+/*!
+ * Configure the IOMUX GPR register to receive shared SDMA UART events
+ *
+ * @param  port         a UART port
+ */
+void config_uartdma_event(int port)
+{
+	return;
+}
+
+/*!
+ * Setup GPIO for USB, Total 34 signals
+ * PIN Configuration for USBOTG:   High/Full speed OTG
+ *	PE2,PE1,PE0,PE24,PE25 -- PRIMARY
+ 	PC7 - PC13  -- PRIMARY
+ 	PB23,PB24 -- PRIMARY
+
+  * PIN Configuration for USBH2:    : High/Full/Low speed host
+  *	PA0 - PA4 -- PRIMARY
+       PD19, PD20,PD21,PD22,PD23,PD24,PD26 --Alternate (SECONDARY)
+
+  * PIN Configuration for USBH1:  Full/low speed host
+  *  PB25 - PB31  -- PRIMARY
+      PB22  -- PRIMARY
+ */
+int gpio_usbh1_active(void)
+{
+	if (gpio_request_mux(MX27_PIN_USBH1_SUSP, GPIO_MUX_PRIMARY) ||
+	    gpio_request_mux(MX27_PIN_USBH1_RCV, GPIO_MUX_PRIMARY) ||
+	    gpio_request_mux(MX27_PIN_USBH1_FS, GPIO_MUX_PRIMARY) ||
+	    gpio_request_mux(MX27_PIN_USBH1_OE_B, GPIO_MUX_PRIMARY) ||
+	    gpio_request_mux(MX27_PIN_USBH1_TXDM, GPIO_MUX_PRIMARY) ||
+	    gpio_request_mux(MX27_PIN_USBH1_TXDP, GPIO_MUX_PRIMARY) ||
+	    gpio_request_mux(MX27_PIN_USBH1_RXDM, GPIO_MUX_PRIMARY) ||
+	    gpio_request_mux(MX27_PIN_USBH1_RXDP, GPIO_MUX_PRIMARY))
+		return -EINVAL;
+
+	//__raw_writew(PBC_BCTRL3_FSH_MOD, PBC_BCTRL3_CLEAR_REG);
+	//__raw_writew(PBC_BCTRL3_FSH_VBUS_EN, PBC_BCTRL3_CLEAR_REG);
+	return 0;
+}
+void gpio_usbh1_inactive(void)
+{
+	gpio_free_mux(MX27_PIN_USBH1_SUSP);
+	gpio_free_mux(MX27_PIN_USBH1_RCV);
+	gpio_free_mux(MX27_PIN_USBH1_FS);
+	gpio_free_mux(MX27_PIN_USBH1_OE_B);
+	gpio_free_mux(MX27_PIN_USBH1_TXDM);
+	gpio_free_mux(MX27_PIN_USBH1_TXDP);
+	gpio_free_mux(MX27_PIN_USBH1_RXDM);
+	gpio_free_mux(MX27_PIN_USBH1_RXDP);
+	//__raw_writew(PBC_BCTRL3_FSH_VBUS_EN, PBC_BCTRL3_SET_REG);
+}
+
+/*
+ * conflicts with CSPI1 (MC13783) and CSPI2 (Connector)
+ */
+int gpio_usbh2_active(void)
+{
+	if (gpio_set_puen(MX27_PIN_USBH2_CLK, 0) ||
+	    gpio_set_puen(MX27_PIN_USBH2_DIR, 0) ||
+	    gpio_set_puen(MX27_PIN_USBH2_DATA7, 0) ||
+	    gpio_set_puen(MX27_PIN_USBH2_NXT, 0) ||
+	    gpio_set_puen(MX27_PIN_USBH2_STP, 0) ||
+	    gpio_set_puen(MX27_PIN_CSPI2_SS2, 0) ||
+	    gpio_set_puen(MX27_PIN_CSPI2_SS1, 0) ||
+	    gpio_set_puen(MX27_PIN_CSPI2_SS0, 0) ||
+	    gpio_set_puen(MX27_PIN_CSPI2_SCLK, 0) ||
+	    gpio_set_puen(MX27_PIN_CSPI2_MISO, 0) ||
+	    gpio_set_puen(MX27_PIN_CSPI2_MOSI, 0) ||
+	    gpio_set_puen(MX27_PIN_CSPI1_SS2, 0))
+		return -EINVAL;
+
+	if (gpio_request_mux(MX27_PIN_USBH2_CLK, GPIO_MUX_PRIMARY) ||
+	    gpio_request_mux(MX27_PIN_USBH2_DIR, GPIO_MUX_PRIMARY) ||
+	    gpio_request_mux(MX27_PIN_USBH2_DATA7, GPIO_MUX_PRIMARY) ||
+	    gpio_request_mux(MX27_PIN_USBH2_NXT, GPIO_MUX_PRIMARY) ||
+	    gpio_request_mux(MX27_PIN_USBH2_STP, GPIO_MUX_PRIMARY) ||
+	    gpio_request_mux(MX27_PIN_CSPI2_SS2, GPIO_MUX_ALT) ||
+	    gpio_request_mux(MX27_PIN_CSPI2_SS1, GPIO_MUX_ALT) ||
+	    gpio_request_mux(MX27_PIN_CSPI2_SS0, GPIO_MUX_ALT) ||
+	    gpio_request_mux(MX27_PIN_CSPI2_SCLK, GPIO_MUX_ALT) ||
+	    gpio_request_mux(MX27_PIN_CSPI2_MISO, GPIO_MUX_ALT) ||
+	    gpio_request_mux(MX27_PIN_CSPI2_MOSI, GPIO_MUX_ALT) ||
+	    gpio_request_mux(MX27_PIN_CSPI1_SS2, GPIO_MUX_ALT))
+		return -EINVAL;
+
+	//__raw_writew(PBC_BCTRL3_HSH_EN, PBC_BCTRL3_CLEAR_REG);
+	return 0;
+}
+void gpio_usbh2_inactive(void)
+{
+	gpio_free_mux(MX27_PIN_USBH2_CLK);
+	gpio_free_mux(MX27_PIN_USBH2_DIR);
+	gpio_free_mux(MX27_PIN_USBH2_DATA7);
+	gpio_free_mux(MX27_PIN_USBH2_NXT);
+	gpio_free_mux(MX27_PIN_USBH2_STP);
+
+	gpio_free_mux(MX27_PIN_CSPI2_SS2);
+	gpio_free_mux(MX27_PIN_CSPI2_SS1);
+	gpio_free_mux(MX27_PIN_CSPI2_SS0);
+	gpio_free_mux(MX27_PIN_CSPI2_SCLK);
+	gpio_free_mux(MX27_PIN_CSPI2_MISO);
+	gpio_free_mux(MX27_PIN_CSPI2_MOSI);
+	gpio_free_mux(MX27_PIN_CSPI1_SS2);
+
+	gpio_set_puen(MX27_PIN_USBH2_CLK, 1);
+	gpio_set_puen(MX27_PIN_USBH2_DIR, 1);
+	gpio_set_puen(MX27_PIN_USBH2_DATA7, 1);
+	gpio_set_puen(MX27_PIN_USBH2_NXT, 1);
+	gpio_set_puen(MX27_PIN_USBH2_STP, 1);
+	gpio_set_puen(MX27_PIN_CSPI2_SS2, 1);
+	gpio_set_puen(MX27_PIN_CSPI2_SS1, 1);
+	gpio_set_puen(MX27_PIN_CSPI2_SS0, 1);
+	gpio_set_puen(MX27_PIN_CSPI2_SCLK, 1);
+	gpio_set_puen(MX27_PIN_CSPI2_MISO, 1);
+	gpio_set_puen(MX27_PIN_CSPI2_MOSI, 1);
+	gpio_set_puen(MX27_PIN_CSPI1_SS2, 1);
+	//__raw_writew(PBC_BCTRL3_HSH_EN, PBC_BCTRL3_SET_REG);
+}
+
+int gpio_usbotg_hs_active(void)
+{
+	if (gpio_request_mux(MX27_PIN_USBOTG_DATA5, GPIO_MUX_PRIMARY) ||
+	    gpio_request_mux(MX27_PIN_USBOTG_DATA6, GPIO_MUX_PRIMARY) ||
+	    gpio_request_mux(MX27_PIN_USBOTG_DATA0, GPIO_MUX_PRIMARY) ||
+	    gpio_request_mux(MX27_PIN_USBOTG_DATA2, GPIO_MUX_PRIMARY) ||
+	    gpio_request_mux(MX27_PIN_USBOTG_DATA1, GPIO_MUX_PRIMARY) ||
+	    gpio_request_mux(MX27_PIN_USBOTG_DATA3, GPIO_MUX_PRIMARY) ||
+	    gpio_request_mux(MX27_PIN_USBOTG_DATA4, GPIO_MUX_PRIMARY) ||
+
+	    gpio_request_mux(MX27_PIN_USBOTG_DIR, GPIO_MUX_PRIMARY) ||
+	    gpio_request_mux(MX27_PIN_USBOTG_STP, GPIO_MUX_PRIMARY) ||
+	    gpio_request_mux(MX27_PIN_USBOTG_NXT, GPIO_MUX_PRIMARY) ||
+	    gpio_request_mux(MX27_PIN_USBOTG_CLK, GPIO_MUX_PRIMARY) ||
+	    gpio_request_mux(MX27_PIN_USBOTG_DATA7, GPIO_MUX_PRIMARY) ||
+
+	    gpio_request_mux(MX27_PIN_USB_OC_B, GPIO_MUX_PRIMARY) ||
+	    gpio_request_mux(MX27_PIN_USB_PWR, GPIO_MUX_PRIMARY))
+		return -EINVAL;
+
+	//__raw_writew(PBC_BCTRL3_OTG_HS_EN, PBC_BCTRL3_CLEAR_REG);
+	//__raw_writew(PBC_BCTRL3_OTG_VBUS_EN, PBC_BCTRL3_CLEAR_REG);
+
+	return 0;
+}
+
+void gpio_usbotg_hs_inactive(void)
+{
+	gpio_free_mux(MX27_PIN_USBOTG_DATA5);
+	gpio_free_mux(MX27_PIN_USBOTG_DATA6);
+	gpio_free_mux(MX27_PIN_USBOTG_DATA0);
+	gpio_free_mux(MX27_PIN_USBOTG_DATA2);
+	gpio_free_mux(MX27_PIN_USBOTG_DATA1);
+	gpio_free_mux(MX27_PIN_USBOTG_DATA3);
+	gpio_free_mux(MX27_PIN_USBOTG_DATA4);
+
+	gpio_free_mux(MX27_PIN_USBOTG_DIR);
+	gpio_free_mux(MX27_PIN_USBOTG_STP);
+	gpio_free_mux(MX27_PIN_USBOTG_NXT);
+	gpio_free_mux(MX27_PIN_USBOTG_CLK);
+	gpio_free_mux(MX27_PIN_USBOTG_DATA7);
+
+	gpio_free_mux(MX27_PIN_USB_OC_B);
+	gpio_free_mux(MX27_PIN_USB_PWR);
+	//__raw_writew(PBC_BCTRL3_OTG_HS_EN, PBC_BCTRL3_SET_REG);
+}
+
+int gpio_usbotg_fs_active(void)
+{
+	return gpio_usbotg_hs_active();
+}
+
+void gpio_usbotg_fs_inactive(void)
+{
+	gpio_usbotg_hs_inactive();
+}
+
+/*!
+ * end Setup GPIO for USB
+ *
+ */
+
+/************************************************************************/
+/* for i2c gpio                                                         */
+/* I2C1:  PD17,PD18 -- Primary 					*/
+/* I2C2:  PC5,PC6    -- Primary					*/
+/************************************************************************/
+/*!
+* Setup GPIO for an I2C device to be active
+*
+* @param  i2c_num         an I2C device
+*/
+void gpio_i2c_active(int i2c_num)
+{
+	switch (i2c_num) {
+	case 0:
+		gpio_request_mux(MX27_PIN_I2C_CLK, GPIO_MUX_PRIMARY);
+		gpio_request_mux(MX27_PIN_I2C_DATA, GPIO_MUX_PRIMARY);
+		break;
+	case 1:
+		gpio_request_mux(MX27_PIN_I2C2_SCL, GPIO_MUX_PRIMARY);
+		gpio_request_mux(MX27_PIN_I2C2_SDA, GPIO_MUX_PRIMARY);
+		break;
+	default:
+		printk(KERN_ERR "gpio_i2c_active no compatible I2C adapter\n");
+		break;
+	}
+}
+
+/*!
+ *  * Setup GPIO for an I2C device to be inactive
+ *   *
+ *    * @param  i2c_num         an I2C device
+ */
+void gpio_i2c_inactive(int i2c_num)
+{
+	switch (i2c_num) {
+	case 0:
+		gpio_free_mux(MX27_PIN_I2C_CLK);
+		gpio_free_mux(MX27_PIN_I2C_DATA);
+		break;
+	case 1:
+		gpio_free_mux(MX27_PIN_I2C2_SCL);
+		gpio_free_mux(MX27_PIN_I2C2_SDA);
+		break;
+	default:
+		break;
+	}
+}
+
+/*!
+ * Setup GPIO for a CSPI device to be active
+ *
+ * @param  cspi_mod         an CSPI device
+ */
+void gpio_spi_active(int cspi_mod)
+{
+	switch (cspi_mod) {
+	case 0:
+		/* SPI1 */
+		gpio_request_mux(MX27_PIN_CSPI1_MOSI, GPIO_MUX_PRIMARY);
+		gpio_request_mux(MX27_PIN_CSPI1_MISO, GPIO_MUX_PRIMARY);
+		gpio_request_mux(MX27_PIN_CSPI1_SCLK, GPIO_MUX_PRIMARY);
+		gpio_request_mux(MX27_PIN_CSPI1_RDY, GPIO_MUX_PRIMARY);
+		gpio_request_mux(MX27_PIN_CSPI1_SS0, GPIO_MUX_PRIMARY);
+		gpio_request_mux(MX27_PIN_CSPI1_SS1, GPIO_MUX_PRIMARY);
+		gpio_request_mux(MX27_PIN_CSPI1_SS2, GPIO_MUX_PRIMARY);
+		break;
+	case 1:
+		/*SPI2  */
+		gpio_request_mux(MX27_PIN_CSPI2_MOSI, GPIO_MUX_PRIMARY);
+		gpio_request_mux(MX27_PIN_CSPI2_MISO, GPIO_MUX_PRIMARY);
+		gpio_request_mux(MX27_PIN_CSPI2_SCLK, GPIO_MUX_PRIMARY);
+		gpio_request_mux(MX27_PIN_CSPI2_SS0, GPIO_MUX_PRIMARY);
+		gpio_request_mux(MX27_PIN_CSPI2_SS1, GPIO_MUX_PRIMARY);
+		gpio_request_mux(MX27_PIN_CSPI2_SS2, GPIO_MUX_PRIMARY);
+		break;
+	case 2:
+		/*SPI3  */
+		gpio_request_mux(MX27_PIN_SD1_D0, GPIO_MUX_ALT);
+		gpio_request_mux(MX27_PIN_SD1_CMD, GPIO_MUX_ALT);
+		gpio_request_mux(MX27_PIN_SD1_CLK, GPIO_MUX_ALT);
+		gpio_request_mux(MX27_PIN_SD1_D3, GPIO_MUX_ALT);
+		break;
+
+	default:
+		break;
+	}
+}
+
+/*!
+ * Setup GPIO for a CSPI device to be inactive
+ *
+ * @param  cspi_mod         a CSPI device
+ */
+void gpio_spi_inactive(int cspi_mod)
+{
+	switch (cspi_mod) {
+	case 0:
+		/* SPI1 */
+		gpio_free_mux(MX27_PIN_CSPI1_MOSI);
+		gpio_free_mux(MX27_PIN_CSPI1_MISO);
+		gpio_free_mux(MX27_PIN_CSPI1_SCLK);
+		gpio_free_mux(MX27_PIN_CSPI1_RDY);
+		gpio_free_mux(MX27_PIN_CSPI1_SS0);
+		gpio_free_mux(MX27_PIN_CSPI1_SS1);
+		gpio_free_mux(MX27_PIN_CSPI1_SS2);
+		break;
+	case 1:
+		/*SPI2  */
+		gpio_free_mux(MX27_PIN_CSPI2_MOSI);
+		gpio_free_mux(MX27_PIN_CSPI2_MISO);
+		gpio_free_mux(MX27_PIN_CSPI2_SCLK);
+		gpio_free_mux(MX27_PIN_CSPI2_SS0);
+		gpio_free_mux(MX27_PIN_CSPI2_SS1);
+		gpio_free_mux(MX27_PIN_CSPI2_SS2);
+		break;
+	case 2:
+		/*SPI3  */
+		gpio_free_mux(MX27_PIN_SD1_D0);
+		gpio_free_mux(MX27_PIN_SD1_CMD);
+		gpio_free_mux(MX27_PIN_SD1_CLK);
+		gpio_free_mux(MX27_PIN_SD1_D3);
+		break;
+
+	default:
+		break;
+	}
+}
+
+/*!
+ * Setup GPIO for a nand flash device to be active
+ *
+ */
+void gpio_nand_active(void)
+{
+	unsigned long reg;
+	//reg = __raw_readl(IO_ADDRESS(SYSCTRL_BASE_ADDR) + SYS_FMCR);
+	//reg &= ~(1 << 4);
+	//__raw_writel(reg, IO_ADDRESS(SYSCTRL_BASE_ADDR) + SYS_FMCR);
+
+	gpio_request_mux(MX27_PIN_NFRB, GPIO_MUX_PRIMARY);
+	gpio_request_mux(MX27_PIN_NFCE_B, GPIO_MUX_PRIMARY);
+	gpio_request_mux(MX27_PIN_NFWP_B, GPIO_MUX_PRIMARY);
+	gpio_request_mux(MX27_PIN_NFCLE, GPIO_MUX_PRIMARY);
+	gpio_request_mux(MX27_PIN_NFALE, GPIO_MUX_PRIMARY);
+	gpio_request_mux(MX27_PIN_NFRE_B, GPIO_MUX_PRIMARY);
+	gpio_request_mux(MX27_PIN_NFWE_B, GPIO_MUX_PRIMARY);
+}
+
+/*!
+ * Setup GPIO for a nand flash device to be inactive
+ *
+ */
+void gpio_nand_inactive(void)
+{
+	gpio_free_mux(MX27_PIN_NFRB);
+	gpio_free_mux(MX27_PIN_NFCE_B);
+	gpio_free_mux(MX27_PIN_NFWP_B);
+	gpio_free_mux(MX27_PIN_NFCLE);
+	gpio_free_mux(MX27_PIN_NFALE);
+	gpio_free_mux(MX27_PIN_NFRE_B);
+	gpio_free_mux(MX27_PIN_NFWE_B);
+}
+
+/*!
+ * Setup GPIO for CSI device to be active
+ *
+ */
+void gpio_sensor_active(void)
+{
+	gpio_request_mux(MX27_PIN_CSI_D0, GPIO_MUX_PRIMARY);
+	gpio_request_mux(MX27_PIN_CSI_D1, GPIO_MUX_PRIMARY);
+	gpio_request_mux(MX27_PIN_CSI_D2, GPIO_MUX_PRIMARY);
+	gpio_request_mux(MX27_PIN_CSI_D3, GPIO_MUX_PRIMARY);
+	gpio_request_mux(MX27_PIN_CSI_D4, GPIO_MUX_PRIMARY);
+	gpio_request_mux(MX27_PIN_CSI_MCLK, GPIO_MUX_PRIMARY);
+	gpio_request_mux(MX27_PIN_CSI_PIXCLK, GPIO_MUX_PRIMARY);
+	gpio_request_mux(MX27_PIN_CSI_D5, GPIO_MUX_PRIMARY);
+	gpio_request_mux(MX27_PIN_CSI_D6, GPIO_MUX_PRIMARY);
+	gpio_request_mux(MX27_PIN_CSI_D7, GPIO_MUX_PRIMARY);
+	gpio_request_mux(MX27_PIN_CSI_VSYNC, GPIO_MUX_PRIMARY);
+	gpio_request_mux(MX27_PIN_CSI_HSYNC, GPIO_MUX_PRIMARY);
+
+#ifdef CONFIG_MXC_CAMERA_MC521DA
+	//__raw_writew(0x100, PBC_BCTRL2_SET_REG);
+#else
+	//__raw_writew(0x400, PBC_BCTRL2_SET_REG);
+#endif
+}
+
+void gpio_sensor_inactive(void)
+{
+	gpio_free_mux(MX27_PIN_CSI_D0);
+	gpio_free_mux(MX27_PIN_CSI_D1);
+	gpio_free_mux(MX27_PIN_CSI_D2);
+	gpio_free_mux(MX27_PIN_CSI_D3);
+	gpio_free_mux(MX27_PIN_CSI_D4);
+	gpio_free_mux(MX27_PIN_CSI_MCLK);
+	gpio_free_mux(MX27_PIN_CSI_PIXCLK);
+	gpio_free_mux(MX27_PIN_CSI_D5);
+	gpio_free_mux(MX27_PIN_CSI_D6);
+	gpio_free_mux(MX27_PIN_CSI_D7);
+	gpio_free_mux(MX27_PIN_CSI_VSYNC);
+	gpio_free_mux(MX27_PIN_CSI_HSYNC);
+
+#ifdef CONFIG_MXC_CAMERA_MC521DA
+	//__raw_writew(0x100, PBC_BCTRL2_CLEAR_REG);
+#else
+	//__raw_writew(0x400, PBC_BCTRL2_CLEAR_REG);
+#endif
+}
+
+void gpio_sensor_reset(bool flag)
+{
+	u16 temp;
+
+	if (flag) {
+		temp = 0x200;
+		//__raw_writew(temp, PBC_BCTRL2_CLEAR_REG);
+	} else {
+		temp = 0x200;
+//		__raw_writew(temp, PBC_BCTRL2_SET_REG);
+	}
+}
+
+/*!
+ * Setup GPIO for LCDC device to be active
+ *
+ */
+void gpio_lcdc_active(void)
+{
+	gpio_request_mux(MX27_PIN_LSCLK, GPIO_MUX_PRIMARY);
+	gpio_request_mux(MX27_PIN_LD0, GPIO_MUX_PRIMARY);
+	gpio_request_mux(MX27_PIN_LD1, GPIO_MUX_PRIMARY);
+	gpio_request_mux(MX27_PIN_LD2, GPIO_MUX_PRIMARY);
+	gpio_request_mux(MX27_PIN_LD3, GPIO_MUX_PRIMARY);
+	gpio_request_mux(MX27_PIN_LD4, GPIO_MUX_PRIMARY);
+	gpio_request_mux(MX27_PIN_LD5, GPIO_MUX_PRIMARY);
+	gpio_request_mux(MX27_PIN_LD6, GPIO_MUX_PRIMARY);
+	gpio_request_mux(MX27_PIN_LD7, GPIO_MUX_PRIMARY);
+	gpio_request_mux(MX27_PIN_LD8, GPIO_MUX_PRIMARY);
+	gpio_request_mux(MX27_PIN_LD9, GPIO_MUX_PRIMARY);
+	gpio_request_mux(MX27_PIN_LD10, GPIO_MUX_PRIMARY);
+	gpio_request_mux(MX27_PIN_LD11, GPIO_MUX_PRIMARY);
+	gpio_request_mux(MX27_PIN_LD12, GPIO_MUX_PRIMARY);
+	gpio_request_mux(MX27_PIN_LD13, GPIO_MUX_PRIMARY);
+	gpio_request_mux(MX27_PIN_LD14, GPIO_MUX_PRIMARY);
+	gpio_request_mux(MX27_PIN_LD15, GPIO_MUX_PRIMARY);
+	gpio_request_mux(MX27_PIN_LD16, GPIO_MUX_PRIMARY);
+	gpio_request_mux(MX27_PIN_LD17, GPIO_MUX_PRIMARY);
+	gpio_request_mux(MX27_PIN_REV, GPIO_MUX_PRIMARY);
+	gpio_request_mux(MX27_PIN_CLS, GPIO_MUX_PRIMARY);
+	gpio_request_mux(MX27_PIN_PS, GPIO_MUX_PRIMARY);
+	gpio_request_mux(MX27_PIN_SPL_SPR, GPIO_MUX_PRIMARY);
+	gpio_request_mux(MX27_PIN_HSYNC, GPIO_MUX_PRIMARY);
+	gpio_request_mux(MX27_PIN_VSYNC, GPIO_MUX_PRIMARY);
+	gpio_request_mux(MX27_PIN_CONTRAST, GPIO_MUX_PRIMARY);
+	gpio_request_mux(MX27_PIN_OE_ACD, GPIO_MUX_PRIMARY);
+}
+
+/*!
+ * Setup GPIO for LCDC device to be inactive
+ *
+ */
+void gpio_lcdc_inactive(void)
+{
+	gpio_free_mux(MX27_PIN_LSCLK);
+	gpio_free_mux(MX27_PIN_LD0);
+	gpio_free_mux(MX27_PIN_LD1);
+	gpio_free_mux(MX27_PIN_LD2);
+	gpio_free_mux(MX27_PIN_LD3);
+	gpio_free_mux(MX27_PIN_LD4);
+	gpio_free_mux(MX27_PIN_LD5);
+	gpio_free_mux(MX27_PIN_LD6);
+	gpio_free_mux(MX27_PIN_LD7);
+	gpio_free_mux(MX27_PIN_LD8);
+	gpio_free_mux(MX27_PIN_LD9);
+	gpio_free_mux(MX27_PIN_LD10);
+	gpio_free_mux(MX27_PIN_LD11);
+	gpio_free_mux(MX27_PIN_LD12);
+	gpio_free_mux(MX27_PIN_LD13);
+	gpio_free_mux(MX27_PIN_LD14);
+	gpio_free_mux(MX27_PIN_LD15);
+	gpio_free_mux(MX27_PIN_LD16);
+	gpio_free_mux(MX27_PIN_LD17);
+	gpio_free_mux(MX27_PIN_REV);
+	gpio_free_mux(MX27_PIN_CLS);
+	gpio_free_mux(MX27_PIN_PS);
+	gpio_free_mux(MX27_PIN_SPL_SPR);
+	gpio_free_mux(MX27_PIN_HSYNC);
+	gpio_free_mux(MX27_PIN_VSYNC);
+	gpio_free_mux(MX27_PIN_CONTRAST);
+	gpio_free_mux(MX27_PIN_OE_ACD);
+}
+
+/*!
+ * Setup GPIO PA25 low to start hard reset FS453 TV encoder
+ *
+ */
+void gpio_fs453_reset_low(void)
+{
+	gpio_free_mux(MX27_PIN_CLS);
+	if (gpio_request_mux(MX27_PIN_CLS, GPIO_MUX_GPIO)) {
+		printk(KERN_ERR "bug: request GPIO PA25 failed.\n");
+		return;
+	}
+
+	/* PA25 (CLS) as output */
+	mxc_set_gpio_direction(MX27_PIN_CLS, 0);
+	gpio_config_mux(MX27_PIN_CLS, GPIO_MUX_GPIO);
+	mxc_set_gpio_dataout(MX27_PIN_CLS, 0);
+}
+
+/*!
+ * Setup GPIO PA25 high to end hard reset FS453 TV encoder
+ *
+ */
+void gpio_fs453_reset_high(void)
+{
+	gpio_free_mux(MX27_PIN_CLS);
+	if (gpio_request_mux(MX27_PIN_CLS, GPIO_MUX_GPIO)) {
+		printk(KERN_ERR "bug: request GPIO PA25 failed.\n");
+		return;
+	}
+
+	/* PA25 (CLS) as output */
+	mxc_set_gpio_direction(MX27_PIN_CLS, 0);
+	gpio_config_mux(MX27_PIN_CLS, GPIO_MUX_GPIO);
+	mxc_set_gpio_dataout(MX27_PIN_CLS, 1);
+}
+
+/*!
+ * This function configures the IOMux block for PMIC standard operations.
+ *
+ */
+void gpio_pmic_active(void)
+{
+	gpio_config_mux(MX27_PIN_TOUT, GPIO_MUX_GPIO);
+	mxc_set_gpio_direction(MX27_PIN_TOUT, 1);
+}
+
+/*!
+ * GPIO settings not required for keypad
+ *
+ */
+void gpio_keypad_active(void)
+{
+}
+
+/*!
+ * GPIO settings not required for keypad
+ *
+ */
+void gpio_keypad_inactive(void)
+{
+}
+
+/*!
+ * Setup GPIO for ATA device to be active
+ *
+ */
+void gpio_ata_active(void)
+{
+	gpio_request_mux(MX27_PIN_ATA_DATA0, GPIO_MUX_PRIMARY);
+	gpio_request_mux(MX27_PIN_ATA_DATA1, GPIO_MUX_PRIMARY);
+	gpio_request_mux(MX27_PIN_ATA_DATA2, GPIO_MUX_PRIMARY);
+	gpio_request_mux(MX27_PIN_ATA_DATA3, GPIO_MUX_PRIMARY);
+	gpio_request_mux(MX27_PIN_ATA_DATA4, GPIO_MUX_PRIMARY);
+	gpio_request_mux(MX27_PIN_ATA_DATA5, GPIO_MUX_PRIMARY);
+	gpio_request_mux(MX27_PIN_ATA_DATA6, GPIO_MUX_PRIMARY);
+	gpio_request_mux(MX27_PIN_ATA_DATA7, GPIO_MUX_PRIMARY);
+	gpio_request_mux(MX27_PIN_ATA_DATA8, GPIO_MUX_PRIMARY);
+	gpio_request_mux(MX27_PIN_ATA_DATA9, GPIO_MUX_PRIMARY);
+	gpio_request_mux(MX27_PIN_ATA_DATA10, GPIO_MUX_PRIMARY);
+	gpio_request_mux(MX27_PIN_ATA_DATA11, GPIO_MUX_PRIMARY);
+	gpio_request_mux(MX27_PIN_ATA_DATA12, GPIO_MUX_PRIMARY);
+	gpio_request_mux(MX27_PIN_ATA_DATA13, GPIO_MUX_PRIMARY);
+	gpio_request_mux(MX27_PIN_ATA_DATA14, GPIO_MUX_PRIMARY);
+	gpio_request_mux(MX27_PIN_ATA_DATA15, GPIO_MUX_PRIMARY);
+
+	gpio_request_mux(MX27_PIN_PC_CD1_B, GPIO_MUX_ALT);
+	gpio_request_mux(MX27_PIN_PC_CD2_B, GPIO_MUX_ALT);
+	gpio_request_mux(MX27_PIN_PC_WAIT_B, GPIO_MUX_ALT);
+	gpio_request_mux(MX27_PIN_PC_READY, GPIO_MUX_ALT);
+	gpio_request_mux(MX27_PIN_PC_PWRON, GPIO_MUX_ALT);
+	gpio_request_mux(MX27_PIN_PC_VS1, GPIO_MUX_ALT);
+	gpio_request_mux(MX27_PIN_PC_VS2, GPIO_MUX_ALT);
+	gpio_request_mux(MX27_PIN_PC_BVD1, GPIO_MUX_ALT);
+	gpio_request_mux(MX27_PIN_PC_BVD2, GPIO_MUX_ALT);
+	gpio_request_mux(MX27_PIN_PC_RST, GPIO_MUX_ALT);
+	gpio_request_mux(MX27_PIN_IOIS16, GPIO_MUX_ALT);
+	gpio_request_mux(MX27_PIN_PC_RW_B, GPIO_MUX_ALT);
+	gpio_request_mux(MX27_PIN_PC_POE, GPIO_MUX_ALT);
+
+	//__raw_writew(PBC_BCTRL2_ATAFEC_EN | PBC_BCTRL2_ATAFEC_SEL |
+	//	     PBC_BCTRL2_ATA_EN, PBC_BCTRL2_CLEAR_REG);
+}
+
+/*!
+ * Setup GPIO for ATA device to be inactive
+ *
+ */
+void gpio_ata_inactive(void)
+{
+	//__raw_writew(PBC_BCTRL2_ATAFEC_EN | PBC_BCTRL2_ATAFEC_SEL |
+	//	     PBC_BCTRL2_ATA_EN, PBC_BCTRL2_SET_REG);
+
+	gpio_free_mux(MX27_PIN_ATA_DATA0);
+	gpio_free_mux(MX27_PIN_ATA_DATA1);
+	gpio_free_mux(MX27_PIN_ATA_DATA2);
+	gpio_free_mux(MX27_PIN_ATA_DATA3);
+	gpio_free_mux(MX27_PIN_ATA_DATA4);
+	gpio_free_mux(MX27_PIN_ATA_DATA5);
+	gpio_free_mux(MX27_PIN_ATA_DATA6);
+	gpio_free_mux(MX27_PIN_ATA_DATA7);
+	gpio_free_mux(MX27_PIN_ATA_DATA8);
+	gpio_free_mux(MX27_PIN_ATA_DATA9);
+	gpio_free_mux(MX27_PIN_ATA_DATA10);
+	gpio_free_mux(MX27_PIN_ATA_DATA11);
+	gpio_free_mux(MX27_PIN_ATA_DATA12);
+	gpio_free_mux(MX27_PIN_ATA_DATA13);
+	gpio_free_mux(MX27_PIN_ATA_DATA14);
+	gpio_free_mux(MX27_PIN_ATA_DATA15);
+
+	gpio_free_mux(MX27_PIN_PC_CD1_B);
+	gpio_free_mux(MX27_PIN_PC_CD2_B);
+	gpio_free_mux(MX27_PIN_PC_WAIT_B);
+	gpio_free_mux(MX27_PIN_PC_READY);
+	gpio_free_mux(MX27_PIN_PC_PWRON);
+	gpio_free_mux(MX27_PIN_PC_VS1);
+	gpio_free_mux(MX27_PIN_PC_VS2);
+	gpio_free_mux(MX27_PIN_PC_BVD1);
+	gpio_free_mux(MX27_PIN_PC_BVD2);
+	gpio_free_mux(MX27_PIN_PC_RST);
+	gpio_free_mux(MX27_PIN_IOIS16);
+	gpio_free_mux(MX27_PIN_PC_RW_B);
+	gpio_free_mux(MX27_PIN_PC_POE);
+}
+
+/*!
+ * Setup GPIO for FEC device to be active
+ *
+ */
+void gpio_fec_active(void)
+{
+	gpio_request_mux(MX27_PIN_ATA_DATA15, GPIO_MUX_OUTPUT1);
+	mxc_set_gpio_direction(MX27_PIN_ATA_DATA15, 0);
+	gpio_request_mux(MX27_PIN_ATA_DATA14, GPIO_MUX_OUTPUT1);
+	mxc_set_gpio_direction(MX27_PIN_ATA_DATA14, 0);
+	gpio_request_mux(MX27_PIN_ATA_DATA13, GPIO_MUX_INPUT1);
+	mxc_set_gpio_direction(MX27_PIN_ATA_DATA13, 1);
+	gpio_request_mux(MX27_PIN_ATA_DATA12, GPIO_MUX_INPUT1);
+	mxc_set_gpio_direction(MX27_PIN_ATA_DATA12, 1);
+	gpio_request_mux(MX27_PIN_ATA_DATA11, GPIO_MUX_INPUT1);
+	mxc_set_gpio_direction(MX27_PIN_ATA_DATA11, 1);
+	gpio_request_mux(MX27_PIN_ATA_DATA10, GPIO_MUX_INPUT1);
+	mxc_set_gpio_direction(MX27_PIN_ATA_DATA10, 1);
+	gpio_request_mux(MX27_PIN_ATA_DATA9, GPIO_MUX_INPUT1);
+	mxc_set_gpio_direction(MX27_PIN_ATA_DATA9, 1);
+	gpio_request_mux(MX27_PIN_ATA_DATA8, GPIO_MUX_INPUT1);
+	mxc_set_gpio_direction(MX27_PIN_ATA_DATA8, 1);
+	gpio_request_mux(MX27_PIN_ATA_DATA7, GPIO_MUX_OUTPUT1);
+	mxc_set_gpio_direction(MX27_PIN_ATA_DATA7, 0);
+
+	gpio_request_mux(MX27_PIN_ATA_DATA6, GPIO_MUX_ALT);
+	gpio_request_mux(MX27_PIN_ATA_DATA5, GPIO_MUX_INPUT1);
+	mxc_set_gpio_direction(MX27_PIN_ATA_DATA5, 1);
+	gpio_request_mux(MX27_PIN_ATA_DATA4, GPIO_MUX_INPUT1);
+	mxc_set_gpio_direction(MX27_PIN_ATA_DATA4, 1);
+	gpio_request_mux(MX27_PIN_ATA_DATA3, GPIO_MUX_INPUT1);
+	mxc_set_gpio_direction(MX27_PIN_ATA_DATA3, 1);
+	gpio_request_mux(MX27_PIN_ATA_DATA2, GPIO_MUX_INPUT1);
+	mxc_set_gpio_direction(MX27_PIN_ATA_DATA2, 1);
+	gpio_request_mux(MX27_PIN_ATA_DATA1, GPIO_MUX_OUTPUT1);
+	mxc_set_gpio_direction(MX27_PIN_ATA_DATA1, 0);
+	gpio_request_mux(MX27_PIN_ATA_DATA0, GPIO_MUX_OUTPUT1);
+	mxc_set_gpio_direction(MX27_PIN_ATA_DATA0, 0);
+	gpio_request_mux(MX27_PIN_SD3_CLK, GPIO_MUX_OUTPUT1);
+	mxc_set_gpio_direction(MX27_PIN_SD3_CLK, 0);
+	gpio_request_mux(MX27_PIN_SD3_CMD, GPIO_MUX_OUTPUT1);
+	mxc_set_gpio_direction(MX27_PIN_SD3_CMD, 0);
+
+	//__raw_writew(PBC_BCTRL2_ATAFEC_EN, PBC_BCTRL2_CLEAR_REG);
+	//__raw_writew(PBC_BCTRL2_ATAFEC_SEL, PBC_BCTRL2_SET_REG);
+}
+
+/*!
+ * Setup GPIO for FEC device to be inactive
+ *
+ */
+void gpio_fec_inactive(void)
+{
+	gpio_free_mux(MX27_PIN_ATA_DATA0);
+	gpio_free_mux(MX27_PIN_ATA_DATA1);
+	gpio_free_mux(MX27_PIN_ATA_DATA2);
+	gpio_free_mux(MX27_PIN_ATA_DATA3);
+	gpio_free_mux(MX27_PIN_ATA_DATA4);
+	gpio_free_mux(MX27_PIN_ATA_DATA5);
+	gpio_free_mux(MX27_PIN_ATA_DATA6);
+	gpio_free_mux(MX27_PIN_ATA_DATA7);
+	gpio_free_mux(MX27_PIN_ATA_DATA8);
+	gpio_free_mux(MX27_PIN_ATA_DATA9);
+	gpio_free_mux(MX27_PIN_ATA_DATA10);
+	gpio_free_mux(MX27_PIN_ATA_DATA11);
+	gpio_free_mux(MX27_PIN_ATA_DATA12);
+	gpio_free_mux(MX27_PIN_ATA_DATA13);
+	gpio_free_mux(MX27_PIN_ATA_DATA14);
+	gpio_free_mux(MX27_PIN_ATA_DATA15);
+
+	gpio_free_mux(MX27_PIN_SD3_CMD);
+	gpio_free_mux(MX27_PIN_SD3_CLK);
+}
+
+/*!
+ * Setup GPIO for SLCDC device to be active
+ *
+ */
+void gpio_slcdc_active(int type)
+{
+	switch (type) {
+	case 0:
+		gpio_request_mux(MX27_PIN_SSI3_CLK, GPIO_MUX_ALT);	/* CLK */
+		gpio_request_mux(MX27_PIN_SSI3_TXDAT, GPIO_MUX_ALT);	/* CS  */
+		gpio_request_mux(MX27_PIN_SSI3_RXDAT, GPIO_MUX_ALT);	/* RS  */
+		gpio_request_mux(MX27_PIN_SSI3_FS, GPIO_MUX_ALT);	/* D0  */
+		break;
+
+	case 1:
+		gpio_request_mux(MX27_PIN_SD2_D1, GPIO_MUX_GPIO);	/* CLK */
+		gpio_request_mux(MX27_PIN_SD2_D2, GPIO_MUX_GPIO);	/* D0  */
+		gpio_request_mux(MX27_PIN_SD2_D3, GPIO_MUX_GPIO);	/* RS  */
+		gpio_request_mux(MX27_PIN_SD2_CMD, GPIO_MUX_GPIO);	/* CS  */
+		break;
+
+	case 2:
+		gpio_request_mux(MX27_PIN_LD0, GPIO_MUX_GPIO);
+		gpio_request_mux(MX27_PIN_LD1, GPIO_MUX_GPIO);
+		gpio_request_mux(MX27_PIN_LD2, GPIO_MUX_GPIO);
+		gpio_request_mux(MX27_PIN_LD3, GPIO_MUX_GPIO);
+		gpio_request_mux(MX27_PIN_LD4, GPIO_MUX_GPIO);
+		gpio_request_mux(MX27_PIN_LD5, GPIO_MUX_GPIO);
+		gpio_request_mux(MX27_PIN_LD6, GPIO_MUX_GPIO);
+		gpio_request_mux(MX27_PIN_LD7, GPIO_MUX_GPIO);
+		gpio_request_mux(MX27_PIN_LD8, GPIO_MUX_GPIO);
+		gpio_request_mux(MX27_PIN_LD9, GPIO_MUX_GPIO);
+		gpio_request_mux(MX27_PIN_LD10, GPIO_MUX_GPIO);
+		gpio_request_mux(MX27_PIN_LD11, GPIO_MUX_GPIO);
+		gpio_request_mux(MX27_PIN_LD12, GPIO_MUX_GPIO);
+		gpio_request_mux(MX27_PIN_LD13, GPIO_MUX_GPIO);
+		gpio_request_mux(MX27_PIN_LD14, GPIO_MUX_GPIO);
+		gpio_request_mux(MX27_PIN_LD15, GPIO_MUX_GPIO);
+		break;
+
+	default:
+		break;
+	}
+
+	return;
+}
+
+/*!
+ * Setup GPIO for SLCDC device to be inactive
+ *
+ */
+void gpio_slcdc_inactive(int type)
+{
+	switch (type) {
+	case 0:
+		gpio_free_mux(MX27_PIN_SSI3_CLK);	/* CLK */
+		gpio_free_mux(MX27_PIN_SSI3_TXDAT);	/* CS  */
+		gpio_free_mux(MX27_PIN_SSI3_RXDAT);	/* RS  */
+		gpio_free_mux(MX27_PIN_SSI3_FS);	/* D0  */
+		break;
+
+	case 1:
+		gpio_free_mux(MX27_PIN_SD2_D1);	/* CLK */
+		gpio_free_mux(MX27_PIN_SD2_D2);	/* D0  */
+		gpio_free_mux(MX27_PIN_SD2_D3);	/* RS  */
+		gpio_free_mux(MX27_PIN_SD2_CMD);	/* CS  */
+		break;
+
+	case 2:
+		gpio_free_mux(MX27_PIN_LD0);
+		gpio_free_mux(MX27_PIN_LD1);
+		gpio_free_mux(MX27_PIN_LD2);
+		gpio_free_mux(MX27_PIN_LD3);
+		gpio_free_mux(MX27_PIN_LD4);
+		gpio_free_mux(MX27_PIN_LD5);
+		gpio_free_mux(MX27_PIN_LD6);
+		gpio_free_mux(MX27_PIN_LD7);
+		gpio_free_mux(MX27_PIN_LD8);
+		gpio_free_mux(MX27_PIN_LD9);
+		gpio_free_mux(MX27_PIN_LD10);
+		gpio_free_mux(MX27_PIN_LD11);
+		gpio_free_mux(MX27_PIN_LD12);
+		gpio_free_mux(MX27_PIN_LD13);
+		gpio_free_mux(MX27_PIN_LD14);
+		gpio_free_mux(MX27_PIN_LD15);
+		break;
+
+	default:
+		break;
+	}
+
+	return;
+}
+
+void gpio_ssi_active(int ssi_num)
+{
+	switch (ssi_num) {
+	case 0:
+		gpio_request_mux(MX27_PIN_SSI1_FS, GPIO_MUX_PRIMARY);
+		gpio_request_mux(MX27_PIN_SSI1_RXDAT, GPIO_MUX_PRIMARY);
+		gpio_request_mux(MX27_PIN_SSI1_TXDAT, GPIO_MUX_PRIMARY);
+		gpio_request_mux(MX27_PIN_SSI1_CLK, GPIO_MUX_PRIMARY);
+		gpio_set_puen(MX27_PIN_SSI1_FS, 0);
+		gpio_set_puen(MX27_PIN_SSI1_RXDAT, 0);
+		gpio_set_puen(MX27_PIN_SSI1_TXDAT, 0);
+		gpio_set_puen(MX27_PIN_SSI1_CLK, 0);
+		break;
+	case 1:
+		gpio_request_mux(MX27_PIN_SSI2_FS, GPIO_MUX_PRIMARY);
+		gpio_request_mux(MX27_PIN_SSI2_RXDAT, GPIO_MUX_PRIMARY);
+		gpio_request_mux(MX27_PIN_SSI2_TXDAT, GPIO_MUX_PRIMARY);
+		gpio_request_mux(MX27_PIN_SSI2_CLK, GPIO_MUX_PRIMARY);
+		gpio_set_puen(MX27_PIN_SSI2_FS, 0);
+		gpio_set_puen(MX27_PIN_SSI2_RXDAT, 0);
+		gpio_set_puen(MX27_PIN_SSI2_TXDAT, 0);
+		gpio_set_puen(MX27_PIN_SSI2_CLK, 0);
+		break;
+	default:
+		break;
+	}
+	return;
+}
+
+/*!
+ *  * Setup GPIO for a SSI port to be inactive
+ *   *
+ *    * @param  ssi_num         an SSI port num
+ */
+
+void gpio_ssi_inactive(int ssi_num)
+{
+	switch (ssi_num) {
+	case 0:
+		gpio_free_mux(MX27_PIN_SSI1_FS);
+		gpio_free_mux(MX27_PIN_SSI1_RXDAT);
+		gpio_free_mux(MX27_PIN_SSI1_TXDAT);
+		gpio_free_mux(MX27_PIN_SSI1_CLK);
+		break;
+	case 1:
+		gpio_free_mux(MX27_PIN_SSI2_FS);
+		gpio_free_mux(MX27_PIN_SSI2_RXDAT);
+		gpio_free_mux(MX27_PIN_SSI2_TXDAT);
+		gpio_free_mux(MX27_PIN_SSI2_CLK);
+		break;
+	default:
+		break;
+	}
+	return;
+}
+
+/*!
+ * Setup GPIO for SDHC to be active
+ *
+ * @param module SDHC module number
+ */
+void gpio_sdhc_active(int module)
+{
+	u16 data;
+	switch (module) {
+	case 0:
+		gpio_request_mux(MX27_PIN_SD1_CLK, GPIO_MUX_PRIMARY);
+		gpio_request_mux(MX27_PIN_SD1_CMD, GPIO_MUX_PRIMARY);
+		gpio_request_mux(MX27_PIN_SD1_D0, GPIO_MUX_PRIMARY);
+		gpio_request_mux(MX27_PIN_SD1_D1, GPIO_MUX_PRIMARY);
+		gpio_request_mux(MX27_PIN_SD1_D2, GPIO_MUX_PRIMARY);
+		gpio_request_mux(MX27_PIN_SD1_D3, GPIO_MUX_PRIMARY);
+		/* 22k pull up for sd1 dat3 pins */
+		//data = __raw_readw(IO_ADDRESS(SYSCTRL_BASE_ADDR + 0x54));
+		//data |= 0x0c;
+		//__raw_writew(data, IO_ADDRESS(SYSCTRL_BASE_ADDR + 0x54));
+		/*mxc_clks_enable(SDHC1_CLK);
+		   mxc_clks_enable(PERCLK2); */
+		break;
+	case 1:
+		gpio_request_mux(MX27_PIN_SD2_CLK, GPIO_MUX_PRIMARY);
+		gpio_request_mux(MX27_PIN_SD2_CMD, GPIO_MUX_PRIMARY);
+		gpio_request_mux(MX27_PIN_SD2_D0, GPIO_MUX_PRIMARY);
+		gpio_request_mux(MX27_PIN_SD2_D1, GPIO_MUX_PRIMARY);
+		gpio_request_mux(MX27_PIN_SD2_D2, GPIO_MUX_PRIMARY);
+		gpio_request_mux(MX27_PIN_SD2_D3, GPIO_MUX_PRIMARY);
+		/* 22k pull up for sd2 pins */
+		//data = __raw_readw(IO_ADDRESS(SYSCTRL_BASE_ADDR + 0x54));
+		//data &= ~0xfff0;
+		//data |= 0xfff0;
+		//__raw_writew(data, IO_ADDRESS(SYSCTRL_BASE_ADDR + 0x54));
+		/*mxc_clks_enable(SDHC2_CLK);
+		   mxc_clks_enable(PERCLK2); */
+		break;
+	case 2:
+		gpio_request_mux(MX27_PIN_SD3_CLK, GPIO_MUX_PRIMARY);
+		gpio_request_mux(MX27_PIN_SD3_CMD, GPIO_MUX_PRIMARY);
+		gpio_request_mux(MX27_PIN_ATA_DATA0, GPIO_MUX_ALT);
+		gpio_request_mux(MX27_PIN_ATA_DATA1, GPIO_MUX_ALT);
+		gpio_request_mux(MX27_PIN_ATA_DATA2, GPIO_MUX_ALT);
+		gpio_request_mux(MX27_PIN_ATA_DATA3, GPIO_MUX_ALT);
+		/*mxc_clks_enable(SDHC3_CLK);
+		   mxc_clks_enable(PERCLK2); */
+		break;
+	default:
+		break;
+	}
+}
+
+/*!
+ * Setup GPIO for SDHC1 to be inactive
+ *
+ * @param module SDHC module number
+ */
+void gpio_sdhc_inactive(int module)
+{
+	switch (module) {
+	case 0:
+		gpio_free_mux(MX27_PIN_SD1_CLK);
+		gpio_free_mux(MX27_PIN_SD1_CMD);
+		gpio_free_mux(MX27_PIN_SD1_D0);
+		gpio_free_mux(MX27_PIN_SD1_D1);
+		gpio_free_mux(MX27_PIN_SD1_D2);
+		gpio_free_mux(MX27_PIN_SD1_D3);
+		/*mxc_clks_disable(SDHC1_CLK); */
+		break;
+	case 1:
+		gpio_free_mux(MX27_PIN_SD2_CLK);
+		gpio_free_mux(MX27_PIN_SD2_CMD);
+		gpio_free_mux(MX27_PIN_SD2_D0);
+		gpio_free_mux(MX27_PIN_SD2_D1);
+		gpio_free_mux(MX27_PIN_SD2_D2);
+		gpio_free_mux(MX27_PIN_SD2_D3);
+		/*mxc_clks_disable(SDHC2_CLK); */
+		break;
+	case 2:
+		gpio_free_mux(MX27_PIN_SD3_CLK);
+		gpio_free_mux(MX27_PIN_SD3_CMD);
+		gpio_free_mux(MX27_PIN_ATA_DATA0);
+		gpio_free_mux(MX27_PIN_ATA_DATA1);
+		gpio_free_mux(MX27_PIN_ATA_DATA2);
+		gpio_free_mux(MX27_PIN_ATA_DATA3);
+		/*mxc_clks_disable(SDHC3_CLK); */
+		break;
+	default:
+		break;
+	}
+}
+
+/*
+ * Probe for the card. If present the GPIO data would be set.
+ */
+int sdhc_get_card_det_status(struct device *dev)
+{
+	return 0;
+}
+
+/*
+ * Return the card detect pin.
+ */
+int sdhc_init_card_det(int id)
+{
+	int ret = 0;
+	switch (id) {
+	case 0:
+		ret = EXPIO_INT_SD1_EN;
+		break;
+	case 1:
+		ret = EXPIO_INT_SD2_EN;
+		break;
+	default:
+		ret = 0;
+		break;
+	}
+	return ret;
+}
+
+/*
+ * Power on/off Sharp QVGA panel.
+ */
+void board_power_lcd(int on)
+{
+	//if (on)
+	//	__raw_writew(PBC_BCTRL1_LCDON, PBC_BCTRL1_SET_REG);
+	//else
+	//	__raw_writew(PBC_BCTRL1_LCDON, PBC_BCTRL1_CLEAR_REG);
+}
+
+void gpio_owire_active(void)
+{
+	gpio_request_mux(MX27_PIN_RTCK, GPIO_MUX_ALT);
+}
+
+void gpio_owire_inactive(void)
+{
+	gpio_request_mux(MX27_PIN_RTCK, GPIO_MUX_PRIMARY);
+}
+
+EXPORT_SYMBOL(gpio_uart_active);
+EXPORT_SYMBOL(gpio_uart_inactive);
+EXPORT_SYMBOL(config_uartdma_event);
+EXPORT_SYMBOL(gpio_usbh1_active);
+EXPORT_SYMBOL(gpio_usbh1_inactive);
+EXPORT_SYMBOL(gpio_usbh2_active);
+EXPORT_SYMBOL(gpio_usbh2_inactive);
+EXPORT_SYMBOL(gpio_usbotg_hs_active);
+EXPORT_SYMBOL(gpio_usbotg_hs_inactive);
+EXPORT_SYMBOL(gpio_usbotg_fs_active);
+EXPORT_SYMBOL(gpio_usbotg_fs_inactive);
+EXPORT_SYMBOL(gpio_i2c_active);
+EXPORT_SYMBOL(gpio_i2c_inactive);
+EXPORT_SYMBOL(gpio_spi_active);
+EXPORT_SYMBOL(gpio_spi_inactive);
+EXPORT_SYMBOL(gpio_nand_active);
+EXPORT_SYMBOL(gpio_nand_inactive);
+EXPORT_SYMBOL(gpio_sensor_active);
+EXPORT_SYMBOL(gpio_sensor_inactive);
+EXPORT_SYMBOL(gpio_sensor_reset);
+EXPORT_SYMBOL(gpio_lcdc_active);
+EXPORT_SYMBOL(gpio_lcdc_inactive);
+EXPORT_SYMBOL(gpio_fs453_reset_low);
+EXPORT_SYMBOL(gpio_fs453_reset_high);
+EXPORT_SYMBOL(gpio_pmic_active);
+EXPORT_SYMBOL(gpio_keypad_active);
+EXPORT_SYMBOL(gpio_keypad_inactive);
+EXPORT_SYMBOL(gpio_ata_active);
+EXPORT_SYMBOL(gpio_ata_inactive);
+EXPORT_SYMBOL(gpio_fec_active);
+EXPORT_SYMBOL(gpio_fec_inactive);
+EXPORT_SYMBOL(gpio_slcdc_active);
+EXPORT_SYMBOL(gpio_slcdc_inactive);
+EXPORT_SYMBOL(gpio_ssi_active);
+EXPORT_SYMBOL(gpio_ssi_inactive);
+EXPORT_SYMBOL(gpio_sdhc_active);
+EXPORT_SYMBOL(gpio_sdhc_inactive);
+EXPORT_SYMBOL(sdhc_get_card_det_status);
+EXPORT_SYMBOL(sdhc_init_card_det);
+EXPORT_SYMBOL(board_power_lcd);
+EXPORT_SYMBOL(gpio_owire_active);
+EXPORT_SYMBOL(gpio_owire_inactive);
diff --git a/include/asm-arm/arch-mxc/memory.h b/include/asm-arm/arch-mxc/memory.h
index 8719da4f2b26..1d291780cb28 100644
--- a/include/asm-arm/arch-mxc/memory.h
+++ b/include/asm-arm/arch-mxc/memory.h
@@ -19,6 +19,10 @@
 #define PHYS_OFFSET             UL(0xA0000000)
 #endif
 
+#ifdef CONFIG_MACH_MX27LITE
+#define PHYS_OFFSET             UL(0xA0000000)
+#endif
+
 #ifndef PHYS_OFFSET
 #define PHYS_OFFSET	        UL(0x80000000)
 #endif