diff options
| author | Robby Cai <R63905@freescale.com> | 2010-12-10 14:15:32 +0800 |
|---|---|---|
| committer | Robby Cai <R63905@freescale.com> | 2010-12-10 15:20:02 +0800 |
| commit | ba0672af160ce5f6eb4342f7acb0bcb0bbb41f0f (patch) | |
| tree | 26368c9b60828e5b7ca801cadcbeffe46dff186b | |
| parent | 92be7f9821a293fb4dc0932263af946d7b81ff89 (diff) | |
ENGR00136202 MX50: Finetune DLL delay paramater for LPDDR2
Changed DLL delay from 0x14 to 0x0b
Swapped pu and (pu+1), pd and (pd+1) assignment in CFG1 and CFG2.
Signed-off-by: Robby Cai <R63905@freescale.com>
| -rw-r--r-- | arch/arm/mach-mx5/mx50_ddr_freq.S | 10 | ||||
| -rw-r--r-- | arch/arm/plat-mxc/zq_calib.c | 33 |
2 files changed, 27 insertions, 16 deletions
diff --git a/arch/arm/mach-mx5/mx50_ddr_freq.S b/arch/arm/mach-mx5/mx50_ddr_freq.S index 3077515ebf76..38317675c52f 100644 --- a/arch/arm/mach-mx5/mx50_ddr_freq.S +++ b/arch/arm/mach-mx5/mx50_ddr_freq.S @@ -645,25 +645,25 @@ tref_done: str r0, [r5, #0x234] ldr r0, =0x60099414 str r0, [r5, #0x238] - ldr r0, =0x000a1401 + ldr r0, =0x000a0b01 str r0, [r5, #0x23c] ldr r0, =0x60099414 str r0, [r5, #0x240] - ldr r0, =0x000a1401 + ldr r0, =0x000a0b01 str r0, [r5, #0x244] ldr r0, =0x60099414 str r0, [r5, #0x248] - ldr r0, =0x000a1401 + ldr r0, =0x000a0b01 str r0, [r5, #0x24c] ldr r0, =0x60099414 str r0, [r5, #0x250] - ldr r0, =0x000a1401 + ldr r0, =0x000a0b01 str r0, [r5, #0x254] ldr r0, =0x60099414 str r0, [r5, #0x258] - ldr r0, =0x000a1401 + ldr r0, =0x000a0b01 str r0, [r5, #0x25c] b Setup_Done diff --git a/arch/arm/plat-mxc/zq_calib.c b/arch/arm/plat-mxc/zq_calib.c index 33e744cfbdaa..bf0a693d9f80 100644 --- a/arch/arm/plat-mxc/zq_calib.c +++ b/arch/arm/plat-mxc/zq_calib.c @@ -69,14 +69,15 @@ static u32 mxc_zq_pu_compare(u32 pu, u32 pd) { u32 data; - /* set PU & PD value */ - data = (pd << 24) | (pu << 16); + /* set PU+1 & PD+1 value + * when pu=0x1F, set (pu+1) = 0x1F + */ + data = ((pd + 1) << 24) | ((pu + 1) << 16); __raw_writel(data, databahn_base + DATABAHN_REG_ZQ_SW_CFG1); /* - * set PU+1 & PD+1 value - * when pu=0x1F, set (pu+1) = 0x1F + * set PU & PD value */ - data = ((pd + 1) << 8) | (pu + 1); + data = (pd << 8) | pu; __raw_writel(data, databahn_base + DATABAHN_REG_ZQ_SW_CFG2); /* * Enable the ZQ comparator, @@ -106,11 +107,11 @@ static u32 mxc_zq_pd_compare(u32 pu, u32 pd) u32 data; /* set bit[4]=1, select PU/PD comparison */ - /* PD range: 0~0xE (0xF has problem, drop it) */ - data = (pd << 24) | (pu << 16) | (1 << 4); + /* PD range: 0~0xF */ + /* when pd=0x0F, set (pd+1) = 0x0F */ + data = ((pd + 1) << 24) | ((pu + 1) << 16) | (1 << 4); __raw_writel(data, databahn_base + DATABAHN_REG_ZQ_SW_CFG1); - /* when pu=0x1F, set (pu+1) = 0x1F */ - data = ((pd + 1) << 8) | (pu + 1); + data = (pd << 8) | pu; __raw_writel(data, databahn_base + DATABAHN_REG_ZQ_SW_CFG2); /* * Enable the ZQ comparator, @@ -175,7 +176,7 @@ static s32 mxc_zq_pd_calib(u32 start, u32 pu) u32 zq_pd_val = 0; /* - * Compare PD from 0 to 0x0E (please ignore 0x0F) + * Compare PD from 0 to 0x0F * data is the result of the comparator * the result sequence looks like: * 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 @@ -225,8 +226,18 @@ static void mxc_zq_hw_load(u32 pu, u32 pd, u32 pu_pd_sel) * When the posedge of bit[4] detected, hardware trigger a load. */ __raw_writel(0x10011, databahn_base + DATABAHN_REG_ZQ_HW_CFG); + /* + * Clear the zq_hw_load bit for next loading + */ __raw_writel(0x10001, databahn_base + DATABAHN_REG_ZQ_HW_CFG); - ndelay(300); + /* + * Delay at least 10us waiting an ddr auto-refresh occurs + * PU PD value are loaded on auto-refresh event + */ + udelay(10); + /* + * Clear the calibration_en (bit[16]) to save power consumption + */ __raw_writel(0x1, databahn_base + DATABAHN_REG_ZQ_HW_CFG); } |