diff options
author | Ed Nash <enash@macbuntu2.(none)> | 2013-07-27 09:24:10 -0400 |
---|---|---|
committer | Ed Nash <enash@macbuntu2.(none)> | 2013-07-27 09:24:10 -0400 |
commit | 93f168cd8bf00be896407108e8bdd761cc97ad9b (patch) | |
tree | fcc4d7f2ffa1ee9393730e21a70f5b0d8be9f34f | |
parent | c4802ad3f3a00ac8f01ad84b84711c942b60cba0 (diff) | |
parent | dea13473ce0c106fc56af798eefc7196bb150695 (diff) |
Merge tag '3.0-vybrid-ts2.6' into ed-mvf
3.0-vybrid-ts2.6
-rw-r--r-- | arch/arm/kernel/sched_clock.c | 1 | ||||
-rw-r--r-- | arch/arm/lib/memset.S | 100 | ||||
-rw-r--r-- | arch/arm/mach-mvf/board-twr-vf700.c | 12 | ||||
-rw-r--r-- | arch/arm/oprofile/common.c | 2 | ||||
-rw-r--r-- | arch/arm/plat-mxc/pit.c | 10 | ||||
-rw-r--r-- | arch/sh/oprofile/common.c | 4 | ||||
-rw-r--r-- | drivers/tty/serial/mvf.c | 235 |
7 files changed, 159 insertions, 205 deletions
diff --git a/arch/arm/kernel/sched_clock.c b/arch/arm/kernel/sched_clock.c index 9a46370fe9da..a481272d7e8a 100644 --- a/arch/arm/kernel/sched_clock.c +++ b/arch/arm/kernel/sched_clock.c @@ -66,6 +66,7 @@ void __init init_sched_clock(struct clock_data *cd, void (*update)(void), * Ensure that sched_clock() starts off at 0ns */ cd->epoch_ns = 0; + cd->epoch_cyc = 0; } void __init sched_clock_postinit(void) diff --git a/arch/arm/lib/memset.S b/arch/arm/lib/memset.S index 650d5923ab83..94b0650ea98f 100644 --- a/arch/arm/lib/memset.S +++ b/arch/arm/lib/memset.S @@ -14,27 +14,15 @@ .text .align 5 - .word 0 - -1: subs r2, r2, #4 @ 1 do we have enough - blt 5f @ 1 bytes to align with? - cmp r3, #2 @ 1 - strltb r1, [r0], #1 @ 1 - strleb r1, [r0], #1 @ 1 - strb r1, [r0], #1 @ 1 - add r2, r2, r3 @ 1 (r2 = r2 - (4 - r3)) -/* - * The pointer is now aligned and the length is adjusted. Try doing the - * memset again. - */ ENTRY(memset) ands r3, r0, #3 @ 1 unaligned? - bne 1b @ 1 + mov ip, r0 @ preserve r0 as return value + bne 6f @ 1 /* - * we know that the pointer in r0 is aligned to a word boundary. + * we know that the pointer in ip is aligned to a word boundary. */ - orr r1, r1, r1, lsl #8 +1: orr r1, r1, r1, lsl #8 orr r1, r1, r1, lsl #16 mov r3, r1 cmp r2, #16 @@ -43,29 +31,28 @@ ENTRY(memset) #if ! CALGN(1)+0 /* - * We need an extra register for this loop - save the return address and - * use the LR + * We need 2 extra registers for this loop - use r8 and the LR */ - str lr, [sp, #-4]! - mov ip, r1 + stmfd sp!, {r8, lr} + mov r8, r1 mov lr, r1 2: subs r2, r2, #64 - stmgeia r0!, {r1, r3, ip, lr} @ 64 bytes at a time. - stmgeia r0!, {r1, r3, ip, lr} - stmgeia r0!, {r1, r3, ip, lr} - stmgeia r0!, {r1, r3, ip, lr} + stmgeia ip!, {r1, r3, r8, lr} @ 64 bytes at a time. + stmgeia ip!, {r1, r3, r8, lr} + stmgeia ip!, {r1, r3, r8, lr} + stmgeia ip!, {r1, r3, r8, lr} bgt 2b - ldmeqfd sp!, {pc} @ Now <64 bytes to go. + ldmeqfd sp!, {r8, pc} @ Now <64 bytes to go. /* * No need to correct the count; we're only testing bits from now on */ tst r2, #32 - stmneia r0!, {r1, r3, ip, lr} - stmneia r0!, {r1, r3, ip, lr} + stmneia ip!, {r1, r3, r8, lr} + stmneia ip!, {r1, r3, r8, lr} tst r2, #16 - stmneia r0!, {r1, r3, ip, lr} - ldr lr, [sp], #4 + stmneia ip!, {r1, r3, r8, lr} + ldmfd sp!, {r8, lr} #else @@ -74,54 +61,63 @@ ENTRY(memset) * whole cache lines at once. */ - stmfd sp!, {r4-r7, lr} + stmfd sp!, {r4-r8, lr} mov r4, r1 mov r5, r1 mov r6, r1 mov r7, r1 - mov ip, r1 + mov r8, r1 mov lr, r1 cmp r2, #96 - tstgt r0, #31 + tstgt ip, #31 ble 3f - and ip, r0, #31 - rsb ip, ip, #32 - sub r2, r2, ip - movs ip, ip, lsl #(32 - 4) - stmcsia r0!, {r4, r5, r6, r7} - stmmiia r0!, {r4, r5} - tst ip, #(1 << 30) - mov ip, r1 - strne r1, [r0], #4 + and r8, ip, #31 + rsb r8, r8, #32 + sub r2, r2, r8 + movs r8, r8, lsl #(32 - 4) + stmcsia ip!, {r4, r5, r6, r7} + stmmiia ip!, {r4, r5} + tst r8, #(1 << 30) + mov r8, r1 + strne r1, [ip], #4 3: subs r2, r2, #64 - stmgeia r0!, {r1, r3-r7, ip, lr} - stmgeia r0!, {r1, r3-r7, ip, lr} + stmgeia ip!, {r1, r3-r8, lr} + stmgeia ip!, {r1, r3-r8, lr} bgt 3b - ldmeqfd sp!, {r4-r7, pc} + ldmeqfd sp!, {r4-r8, pc} tst r2, #32 - stmneia r0!, {r1, r3-r7, ip, lr} + stmneia ip!, {r1, r3-r8, lr} tst r2, #16 - stmneia r0!, {r4-r7} - ldmfd sp!, {r4-r7, lr} + stmneia ip!, {r4-r7} + ldmfd sp!, {r4-r8, lr} #endif 4: tst r2, #8 - stmneia r0!, {r1, r3} + stmneia ip!, {r1, r3} tst r2, #4 - strne r1, [r0], #4 + strne r1, [ip], #4 /* * When we get here, we've got less than 4 bytes to zero. We * may have an unaligned pointer as well. */ 5: tst r2, #2 - strneb r1, [r0], #1 - strneb r1, [r0], #1 + strneb r1, [ip], #1 + strneb r1, [ip], #1 tst r2, #1 - strneb r1, [r0], #1 + strneb r1, [ip], #1 mov pc, lr + +6: subs r2, r2, #4 @ 1 do we have enough + blt 5b @ 1 bytes to align with? + cmp r3, #2 @ 1 + strltb r1, [ip], #1 @ 1 + strleb r1, [ip], #1 @ 1 + strb r1, [ip], #1 @ 1 + add r2, r2, r3 @ 1 (r2 = r2 - (4 - r3)) + b 1b ENDPROC(memset) diff --git a/arch/arm/mach-mvf/board-twr-vf700.c b/arch/arm/mach-mvf/board-twr-vf700.c index 01fd4dc364cc..becf814e3a11 100644 --- a/arch/arm/mach-mvf/board-twr-vf700.c +++ b/arch/arm/mach-mvf/board-twr-vf700.c @@ -196,11 +196,15 @@ static iomux_v3_cfg_t mvf600_pads[] = { MVF600_PAD24_PTB2_FTM0CH2, MVF600_PAD25_PTB3_FTM0CH3, - MVF600_PAD28_PTB6_FTM0CH6, - MVF600_PAD29_PTB7_FTM0CH7, + /* + * PTB6 & PTB7 are commented out as they conflict with uart2 + * which is the MQX default console (e.g for printf) + */ + /* MVF600_PAD28_PTB6_FTM0CH6, */ + /* MVF600_PAD29_PTB7_FTM0CH7, */ + /*MVF600_PAD30_PTB8_FTM1CH0,*/ MVF600_PAD31_PTB9_FTM1CH1, - /* Touch Screen */ MVF600_PAD21_PTA31_TS_IRQ, @@ -388,6 +392,8 @@ static struct mvf_dcu_platform_data mvf_dcu_pdata = { static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags, char **cmdline, struct meminfo *mi) { + if (!mi->nr_banks) + arm_add_memory(PHYS_OFFSET, SZ_128M); } /* * Not defined the cd/wp so far, set it always present for debug*/ diff --git a/arch/arm/oprofile/common.c b/arch/arm/oprofile/common.c index c074e66ad224..4e0a371630b3 100644 --- a/arch/arm/oprofile/common.c +++ b/arch/arm/oprofile/common.c @@ -116,7 +116,7 @@ int __init oprofile_arch_init(struct oprofile_operations *ops) return oprofile_perf_init(ops); } -void __exit oprofile_arch_exit(void) +void oprofile_arch_exit(void) { oprofile_perf_exit(); } diff --git a/arch/arm/plat-mxc/pit.c b/arch/arm/plat-mxc/pit.c index 1e350b950b9f..30b581bef12e 100644 --- a/arch/arm/plat-mxc/pit.c +++ b/arch/arm/plat-mxc/pit.c @@ -92,14 +92,18 @@ static DEFINE_CLOCK_DATA(cd); static void __iomem *sched_clock_reg; unsigned long long notrace sched_clock(void) { - cycle_t cyc = sched_clock_reg ? ((u32)~0 - - __raw_readl(sched_clock_reg)) : 0; + cycle_t cyc = 0; + + if (sched_clock_reg) + cyc = pit_cnt + pit_cycle_per_jiffy - __raw_readl(sched_clock_reg); return cyc_to_sched_clock(&cd, cyc, (u32)~0); } static void notrace mvf_update_sched_clock(void) { - cycle_t cyc = sched_clock_reg ? __raw_readl(sched_clock_reg) : 0; + cycle_t cyc = sched_clock_reg ? (pit_cnt + pit_cycle_per_jiffy - + __raw_readl(sched_clock_reg)) : 0; + update_sched_clock(&cd, cyc, (u32)~0); } static int __init pit_clocksource_init(struct clk *timer_clk) diff --git a/arch/sh/oprofile/common.c b/arch/sh/oprofile/common.c index b4c2d2b946dd..e4dd5d5a1115 100644 --- a/arch/sh/oprofile/common.c +++ b/arch/sh/oprofile/common.c @@ -49,7 +49,7 @@ int __init oprofile_arch_init(struct oprofile_operations *ops) return oprofile_perf_init(ops); } -void __exit oprofile_arch_exit(void) +void oprofile_arch_exit(void) { oprofile_perf_exit(); kfree(sh_pmu_op_name); @@ -60,5 +60,5 @@ int __init oprofile_arch_init(struct oprofile_operations *ops) ops->backtrace = sh_backtrace; return -ENODEV; } -void __exit oprofile_arch_exit(void) {} +void oprofile_arch_exit(void) {} #endif /* CONFIG_HW_PERF_EVENTS */ diff --git a/drivers/tty/serial/mvf.c b/drivers/tty/serial/mvf.c index cb0e98ffb527..814a7daa56f0 100644 --- a/drivers/tty/serial/mvf.c +++ b/drivers/tty/serial/mvf.c @@ -74,7 +74,6 @@ struct imx_port { struct uart_port port; struct timer_list timer; unsigned int old_status; - int txirq, rxirq, rtsirq; unsigned int have_rtscts:1; unsigned int use_dcedte:1; unsigned int use_irda:1; @@ -104,12 +103,6 @@ struct imx_port { wait_queue_head_t dma_wait; }; -#ifdef CONFIG_IRDA -#define USE_IRDA(sport) ((sport)->use_irda) -#else -#define USE_IRDA(sport) (0) -#endif - /* * Handle any change of modem status signal since we were last called. */ @@ -192,11 +185,10 @@ static void imx_stop_rx(struct uart_port *port) */ static void imx_enable_ms(struct uart_port *port) { -#if 0 - struct imx_port *sport = (struct imx_port *)port; - - mod_timer(&sport->timer, jiffies); -#endif + /* + * To Be Implemented + */ + return ; } static inline void imx_transmit_buffer(struct imx_port *sport) @@ -215,7 +207,12 @@ static inline void imx_transmit_buffer(struct imx_port *sport) } if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) + { + if (sport->port.state->port.tty) + { uart_write_wakeup(&sport->port); + } + } if (uart_circ_empty(xmit)) imx_stop_tx(&sport->port); @@ -304,7 +301,12 @@ static void dma_tx_work(struct work_struct *w) spin_unlock_irqrestore(&sport->port.lock, flags); if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) + { + if (sport->port.state->port.tty) + { uart_write_wakeup(&sport->port); + } + } return; } @@ -317,35 +319,12 @@ static void imx_start_tx(struct uart_port *port) { struct imx_port *sport = (struct imx_port *)port; unsigned char temp; -#if 0 - if (USE_IRDA(sport)) { - /* half duplex in IrDA mode; have to disable receive mode */ - temp = readl(sport->port.membase + UCR4); - temp &= ~(UCR4_DREN); - writel(temp, sport->port.membase + UCR4); - - temp = readl(sport->port.membase + UCR1); - temp &= ~(UCR1_RRDYEN); - writel(temp, sport->port.membase + UCR1); - } -#endif + if (!sport->enable_dma) { temp = readb(sport->port.membase + MXC_UARTCR2); writeb(temp | MXC_UARTCR2_TIE, sport->port.membase + MXC_UARTCR2); } -#if 0 - if (USE_IRDA(sport)) { - temp = readl(sport->port.membase + UCR1); - temp |= UCR1_TRDYEN; - writel(temp, sport->port.membase + UCR1); - - temp = readl(sport->port.membase + UCR4); - temp |= UCR4_TCEN; - writel(temp, sport->port.membase + UCR4); - } -#endif - if (sport->enable_dma) { schedule_work(&sport->tsk_dma_tx); return; @@ -377,7 +356,12 @@ static irqreturn_t imx_txint(int irq, void *dev_id) imx_transmit_buffer(sport); if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) + { + if (sport->port.state->port.tty) + { uart_write_wakeup(&sport->port); + } + } out: spin_unlock_irqrestore(&sport->port.lock, flags); @@ -462,6 +446,7 @@ static irqreturn_t imx_rxint(int irq, void *dev_id) out: spin_unlock_irqrestore(&sport->port.lock, flags); + //TODO: Check tsk_rx, seems to be edma related. schedule_work(&sport->tsk_rx); return IRQ_HANDLED; } @@ -521,11 +506,14 @@ static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl) unsigned long temp; temp = readb(sport->port.membase + MXC_UARTMODEM) & - ~MXC_UARTMODEM_RXRTSE; + ~(MXC_UARTMODEM_RXRTSE | MXC_UARTMODEM_TXCTSE); if (mctrl & TIOCM_RTS) temp |= MXC_UARTMODEM_RXRTSE; + if (mctrl & TIOCM_CTS) + temp |= MXC_UARTMODEM_TXCTSE; + writeb(temp, sport->port.membase + MXC_UARTMODEM); } @@ -539,7 +527,6 @@ static void imx_break_ctl(struct uart_port *port, int break_state) unsigned char temp; spin_lock_irqsave(&sport->port.lock, flags); - temp = readb(sport->port.membase + MXC_UARTCR2) & ~MXC_UARTCR2_SBK; if (break_state != 0) @@ -584,7 +571,6 @@ static int imx_setup_watermark(struct imx_port *sport, unsigned int mode) /* restore CR2 */ writeb(old_cr2, sport->port.membase + MXC_UARTCR2); - return 0; } @@ -605,27 +591,6 @@ static int imx_startup(struct uart_port *port) imx_setup_watermark(sport, 0); #endif - /* disable the DREN bit (Data Ready interrupt enable) before - * requesting IRQs - */ - temp = readb(sport->port.membase + MXC_UARTCR2); - - writeb(temp & ~MXC_UARTCR2_RIE, sport->port.membase + MXC_UARTCR2); - - if (USE_IRDA(sport)) { - /* reset fifo's and state machines */ -#if 0 - int i = 100; - temp = readl(sport->port.membase + UCR2); - temp &= ~UCR2_SRST; - writel(temp, sport->port.membase + UCR2); - while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && - (--i > 0)) { - udelay(1); - } -#endif - } - /* * Allocate the IRQ(s) * Vybrid chips only have one interrupt. @@ -633,8 +598,7 @@ static int imx_startup(struct uart_port *port) retval = request_irq(sport->port.irq, imx_int, 0, DRIVER_NAME, sport); if (retval) { - free_irq(sport->port.irq, sport); - goto error_out1; + return retval; } /* Enable the DMA ops for uart. */ @@ -659,24 +623,18 @@ static int imx_startup(struct uart_port *port) spin_lock_irqsave(&sport->port.lock, flags); /* - * Finally, clear and enable interrupts + * Finally enable interrupts and RX/TX */ - temp = readb(sport->port.membase + MXC_UARTCR2); - temp |= MXC_UARTCR2_RIE | MXC_UARTCR2_TIE; + temp |= (MXC_UARTCR2_RIE | MXC_UARTCR2_TIE | MXC_UARTCR2_TE | MXC_UARTCR2_RE); writeb(temp, sport->port.membase + MXC_UARTCR2); - /* - * Enable modem status interrupts - */ + spin_unlock_irqrestore(&sport->port.lock, flags); tty = sport->port.state->port.tty; return 0; - -error_out1: - return retval; } static void imx_shutdown(struct uart_port *port) @@ -694,9 +652,14 @@ static void imx_shutdown(struct uart_port *port) } } + while (!(readb(sport->port.membase + MXC_UARTSR1) & MXC_UARTSR1_TC)) + barrier(); spin_lock_irqsave(&sport->port.lock, flags); + + /* Disable Rx/Tx and interrupts */ temp = readb(sport->port.membase + MXC_UARTCR2); - temp &= ~(MXC_UARTCR2_TE | MXC_UARTCR2_RE); + temp &= ~(MXC_UARTCR2_TE | MXC_UARTCR2_RE | + MXC_UARTCR2_TIE | MXC_UARTCR2_TCIE | MXC_UARTCR2_RIE); writeb(temp, sport->port.membase + MXC_UARTCR2); spin_unlock_irqrestore(&sport->port.lock, flags); @@ -704,24 +667,9 @@ static void imx_shutdown(struct uart_port *port) /* * Free the interrupts */ - if (sport->txirq > 0) { - if (!USE_IRDA(sport)) - free_irq(sport->rtsirq, sport); - free_irq(sport->txirq, sport); - free_irq(sport->rxirq, sport); - } else - free_irq(sport->port.irq, sport); - /* - * Disable all interrupts, port and break condition. - */ + free_irq(sport->port.irq, sport); - spin_lock_irqsave(&sport->port.lock, flags); - temp = readb(sport->port.membase + MXC_UARTCR2); - temp &= ~(MXC_UARTCR2_TIE | MXC_UARTCR2_TCIE | MXC_UARTCR2_RIE); - writeb(temp, sport->port.membase + MXC_UARTCR2); - - spin_unlock_irqrestore(&sport->port.lock, flags); } static void @@ -740,14 +688,6 @@ imx_set_termios(struct uart_port *port, struct ktermios *termios, cr4 = readb(sport->port.membase + MXC_UARTCR4); bdh = readb(sport->port.membase + MXC_UARTBDH); modem = readb(sport->port.membase + MXC_UARTMODEM); - /* - * If we don't support modem control lines, don't allow - * these to be set. - */ - if (0) { - termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR); - termios->c_cflag |= CLOCAL; - } /* * We only support CS8 and CS7,but CS7 must enable PE. @@ -847,10 +787,10 @@ imx_set_termios(struct uart_port *port, struct ktermios *termios, while (!(readb(sport->port.membase + MXC_UARTSR1) & MXC_UARTSR1_TC)) barrier(); + /* disable transmit and receive */ writeb(old_cr2 & ~(MXC_UARTCR2_TE | MXC_UARTCR2_RE), sport->port.membase + MXC_UARTCR2); - /* disable transmit and receive */ sbr = sport->port.uartclk / (16 * baud); brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2)/baud; @@ -1094,6 +1034,7 @@ imx_console_write(struct console *co, const char *s, unsigned int count) unsigned long flags; spin_lock_irqsave(&sport->port.lock, flags); + /* * First, save UCR1/2 and then disable interrupts */ @@ -1113,9 +1054,10 @@ imx_console_write(struct console *co, const char *s, unsigned int count) * and restore CR2 */ while (!(readb(sport->port.membase + MXC_UARTSR1) & MXC_UARTSR1_TC)) - ; + barrier(); writeb(old_cr2, sport->port.membase + MXC_UARTCR2); + spin_unlock_irqrestore(&sport->port.lock, flags); } @@ -1127,49 +1069,50 @@ static void __init imx_console_get_options(struct imx_port *sport, int *baud, int *parity, int *bits) { + unsigned char cr1, cr2, bdh, bdl, brfa; + unsigned int sbr, uartclk; + unsigned int baud_raw; - if (readb(sport->port.membase + MXC_UARTCR2) & - (MXC_UARTCR2_TE | MXC_UARTCR2)) { - /* ok, the port was enabled */ - unsigned char cr1, bdh, bdl, brfa; - unsigned int sbr, uartclk; - unsigned int baud_raw; - - cr1 = readb(sport->port.membase + MXC_UARTCR1); + cr2 = readb(sport->port.membase + MXC_UARTCR2); + cr2 &= (MXC_UARTCR2_TE | MXC_UARTCR2_RE); + if (!cr2) + return; + /* ok, the port was enabled */ - *parity = 'n'; - if (cr1 & MXC_UARTCR1_PE) { - if (cr1 & MXC_UARTCR1_PT) - *parity = 'o'; - else - *parity = 'e'; - } + cr1 = readb(sport->port.membase + MXC_UARTCR1); - if (cr1 & MXC_UARTCR1_M) - *bits = 9; + *parity = 'n'; + if (cr1 & MXC_UARTCR1_PE) { + if (cr1 & MXC_UARTCR1_PT) + *parity = 'o'; else - *bits = 8; - - bdh = readb(sport->port.membase + MXC_UARTBDH) & - MXC_UARTBDH_SBR_MASK; - bdl = readb(sport->port.membase + MXC_UARTBDL); - sbr = bdh; - sbr <<= 8; - sbr |= bdl; - brfa = readb(sport->port.membase + MXC_UARTCR4) & - MXC_UARTCR4_BRFA_MASK; - - uartclk = clk_get_rate(sport->clk); - /* - * Baud = mod_clk/(16*(sbr[13]+(brfa)/32) - */ - baud_raw = uartclk/(16 * (sbr + brfa/32)); - - if (*baud != baud_raw) - printk(KERN_INFO "Serial: Console IMX " - "rounded baud rate from %d to %d\n", - baud_raw, *baud); + *parity = 'e'; } + + if (cr1 & MXC_UARTCR1_M) + *bits = 9; + else + *bits = 8; + + bdh = readb(sport->port.membase + MXC_UARTBDH) & + MXC_UARTBDH_SBR_MASK; + bdl = readb(sport->port.membase + MXC_UARTBDL); + sbr = bdh; + sbr <<= 8; + sbr |= bdl; + brfa = readb(sport->port.membase + MXC_UARTCR4) & + MXC_UARTCR4_BRFA_MASK; + + uartclk = clk_get_rate(sport->clk); + /* + * Baud = mod_clk/(16*(sbr[13]+(brfa)/32) + */ + baud_raw = uartclk/(16 * (sbr + brfa/32)); + + if (*baud != baud_raw) + printk(KERN_INFO "Serial: Console IMX " + "rounded baud rate from %d to %d\n", + baud_raw, *baud); } static int __init @@ -1288,9 +1231,6 @@ static int serial_imx_probe(struct platform_device *pdev) sport->port.ops = &imx_pops; sport->port.flags = UPF_BOOT_AUTOCONF; sport->port.line = pdev->id; - init_timer(&sport->timer); - sport->timer.function = imx_timeout; - sport->timer.data = (unsigned long)sport; sport->clk = clk_get(&pdev->dev, "mvf-uart.1"); if (IS_ERR(sport->clk)) { @@ -1305,18 +1245,25 @@ static int serial_imx_probe(struct platform_device *pdev) pdata = pdev->dev.platform_data; if (pdata && (pdata->flags & IMXUART_HAVE_RTSCTS)) + { sport->have_rtscts = 1; + printk("IMX UART RTS/CTS enabled\n"); + } if (pdata && (pdata->flags & IMXUART_USE_DCEDTE)) + { sport->use_dcedte = 1; + printk("IMX UART using DCE/DTE\n"); + } if (pdata && (pdata->flags & IMXUART_EDMA)) + { sport->enable_dma = 1; + printk("IMX UART EDMA enabled\n"); + } if (pdata && (pdata->flags & IMXUART_FIFO)) + { sport->fifo_en = 1; - -#ifdef CONFIG_IRDA - if (pdata && (pdata->flags & IMXUART_IRDA)) - sport->use_irda = 1; -#endif + printk("IMX UART FIFO enabled\n"); + } if (pdata && pdata->init) { ret = pdata->init(pdev); |