ARM: Tegra: Roth: Merge rel-roth to main

Change-Id: I52181799337f4e2ee735f3f148b8f661cebbe0f0
Signed-off-by: Matt Wagner <mwagner@nvidia.com>
Reviewed-on: http://git-master/r/242147
Reviewed-by: Tao Xie <txie@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

7 files changed, 113 insertions, 2683 deletions

diff --git a/arch/arm/mach-tegra/board-roth-fan.c b/arch/arm/mach-tegra/board-roth-fan.c
index 12891a3db0c9..8ba5f7e98426 100644
--- a/arch/arm/mach-tegra/board-roth-fan.c
+++ b/arch/arm/mach-tegra/board-roth-fan.c
@@ -52,10 +52,6 @@ static struct platform_device pwm_fan_therm_cooling_device = {
 	},
 };
 
-static struct platform_device *roth_fan_device[] = {
-	&tegra_pwfm_device,
-};
-
 int __init roth_fan_init(void)
 {
 	int err;
@@ -67,12 +63,5 @@ int __init roth_fan_init(void)
 	}
 	gpio_free(TEGRA_GPIO_PU3);
 	platform_device_register(&pwm_fan_therm_cooling_device);
-
-	err = platform_add_devices(roth_fan_device,
-				ARRAY_SIZE(roth_fan_device));
-	if (err < 0) {
-		pr_err("FAN:pwm fan device device registration failed\n");
-		return err;
-	}
 	return 0;
 }
diff --git a/arch/arm/mach-tegra/board-roth-kbc.c b/arch/arm/mach-tegra/board-roth-kbc.c
index 8fd370ef5ee7..a563b66d047b 100644
--- a/arch/arm/mach-tegra/board-roth-kbc.c
+++ b/arch/arm/mach-tegra/board-roth-kbc.c
@@ -56,12 +56,21 @@
 		.debounce_interval = _deb,	\
 	}
 
-/* Make KEY_POWER to index 0 only */
-static struct gpio_keys_button roth_p2454_keys[] = {
-	[0] = GPIO_KEY(KEY_POWER, PR0, 0),
-	[1] = GPIO_KEY(KEY_VOLUMEUP, PR2, 0),
-	[2] = GPIO_KEY(KEY_VOLUMEDOWN, PR1, 0),
+static struct gpio_keys_button roth_gpio_keys[] = {
+	[0] = GPIO_KEY(KEY_POWER, PQ0, 1),
+	[1] = GPIO_KEY(KEY_BACK, PR2, 0),
+	[2] = GPIO_KEY(KEY_HOME, PR1, 0),
 	[3] = {
+		.code = KEY_WAKEUP,
+		.gpio = TEGRA_GPIO_PI5,
+		.irq = -1,
+		.type = EV_KEY,
+		.desc = "Controller",
+		.active_low = 0,
+		.wakeup = 1,
+		.debounce_interval = 10,
+	},
+	[4] = {
 		.code = SW_LID,
 		.gpio = TEGRA_GPIO_HALL,
 		.irq = -1,
@@ -80,33 +89,35 @@ static int roth_wakeup_key(void)
 		| (u64)readl(IO_ADDRESS(TEGRA_PMC_BASE)
 		+ PMC_WAKE2_STATUS) << 32;
 
-	if (status & ((u64)1 << TEGRA_WAKE_GPIO_PQ0))
+	if (status & (1ULL << TEGRA_WAKE_GPIO_PQ0))
 		wakeup_key = KEY_POWER;
-	else if (status & ((u64)1 << TEGRA_WAKE_GPIO_PS0))
+	else if (status & (1ULL << TEGRA_WAKE_GPIO_PI5))
+		wakeup_key = KEY_WAKEUP;
+	else if (status & (1ULL << TEGRA_WAKE_GPIO_PS0))
 		wakeup_key = SW_LID;
 	else
-		wakeup_key = KEY_RESERVED;
+		wakeup_key = -1;
 
 	return wakeup_key;
 }
 
-static struct gpio_keys_platform_data roth_p2454_keys_pdata = {
-	.buttons	= roth_p2454_keys,
-	.nbuttons	= ARRAY_SIZE(roth_p2454_keys),
+static struct gpio_keys_platform_data roth_gpio_keys_pdata = {
+	.buttons	= roth_gpio_keys,
+	.nbuttons	= ARRAY_SIZE(roth_gpio_keys),
 	.wakeup_key	= roth_wakeup_key,
 };
 
-static struct platform_device roth_p2454_keys_device = {
+static struct platform_device roth_gpio_keys_device = {
 	.name	= "gpio-keys",
 	.id	= 0,
 	.dev	= {
-		.platform_data  = &roth_p2454_keys_pdata,
+		.platform_data  = &roth_gpio_keys_pdata,
 	},
 };
 
 int __init roth_kbc_init(void)
 {
-	platform_device_register(&roth_p2454_keys_device);
+	platform_device_register(&roth_gpio_keys_device);
 	return 0;
 }
 
diff --git a/arch/arm/mach-tegra/board-roth-memory.c b/arch/arm/mach-tegra/board-roth-memory.c
index 8667b356a924..7acab5c29629 100644
--- a/arch/arm/mach-tegra/board-roth-memory.c
+++ b/arch/arm/mach-tegra/board-roth-memory.c
@@ -23,2564 +23,11 @@
 #include "board.h"
 #include "board-roth.h"
 
-#include "tegra-board-id.h"
 #include "tegra11_emc.h"
 #include "fuse.h"
 #include "devices.h"
 
-static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = {
-	{
-		0x41,       /* Rev 4.0.3 */
-		12750,      /* SDRAM frequency */
-		900,       /* min voltage */
-		"pll_p",    /* clock source id */
-		0x4000003e, /* CLK_SOURCE_EMC */
-		99,         /* number of burst_regs */
-		30,         /* number of trim_regs (each channel) */
-		11,         /* number of up_down_regs */
-		{
-			0x00000000, /* EMC_RC */
-			0x00000003, /* EMC_RFC */
-			0x00000000, /* EMC_RFC_SLR */
-			0x00000000, /* EMC_RAS */
-			0x00000000, /* EMC_RP */
-			0x00000004, /* EMC_R2W */
-			0x0000000a, /* EMC_W2R */
-			0x00000003, /* EMC_R2P */
-			0x0000000b, /* EMC_W2P */
-			0x00000000, /* EMC_RD_RCD */
-			0x00000000, /* EMC_WR_RCD */
-			0x00000003, /* EMC_RRD */
-			0x00000001, /* EMC_REXT */
-			0x00000000, /* EMC_WEXT */
-			0x00000005, /* EMC_WDV */
-			0x0000000f, /* EMC_WDV_MASK */
-			0x00000005, /* EMC_IBDLY */
-			0x00010000, /* EMC_PUTERM_EXTRA */
-			0x00000000, /* EMC_CDB_CNTL_2 */
-			0x00000004, /* EMC_QRST */
-			0x0000000e, /* EMC_RDV_MASK */
-			0x00000060, /* EMC_REFRESH */
-			0x00000000, /* EMC_BURST_REFRESH_NUM */
-			0x00000018, /* EMC_PRE_REFRESH_REQ_CNT */
-			0x00000002, /* EMC_PDEX2WR */
-			0x00000002, /* EMC_PDEX2RD */
-			0x00000001, /* EMC_PCHG2PDEN */
-			0x00000000, /* EMC_ACT2PDEN */
-			0x00000007, /* EMC_AR2PDEN */
-			0x0000000f, /* EMC_RW2PDEN */
-			0x00000005, /* EMC_TXSR */
-			0x00000005, /* EMC_TXSRDLL */
-			0x00000004, /* EMC_TCKE */
-			0x00000004, /* EMC_TCKESR */
-			0x00000004, /* EMC_TPD */
-			0x00000004, /* EMC_TFAW */
-			0x00000000, /* EMC_TRPAB */
-			0x00000004, /* EMC_TCLKSTABLE */
-			0x00000005, /* EMC_TCLKSTOP */
-			0x00000064, /* EMC_TREFBW */
-			0x00000005, /* EMC_QUSE_EXTRA */
-			0x00000020, /* EMC_ODT_WRITE */
-			0x00000000, /* EMC_ODT_READ */
-			0x0000aa88, /* EMC_FBIO_CFG5 */
-			0x002c00a0, /* EMC_CFG_DIG_DLL */
-			0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
-			0x00070000, /* EMC_DLL_XFORM_DQS4 */
-			0x00070000, /* EMC_DLL_XFORM_DQS5 */
-			0x00070000, /* EMC_DLL_XFORM_DQS6 */
-			0x00070000, /* EMC_DLL_XFORM_DQS7 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE4 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE5 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE6 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE7 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
-			0x001112a0, /* EMC_XM2CMDPADCTRL */
-			0x00000000, /* EMC_XM2CMDPADCTRL4 */
-			0x0000a11c, /* EMC_XM2DQSPADCTRL2 */
-			0x00000000, /* EMC_XM2DQPADCTRL2 */
-			0x77ffc085, /* EMC_XM2CLKPADCTRL */
-			0x81f1f108, /* EMC_XM2COMPPADCTRL */
-			0x03035504, /* EMC_XM2VTTGENPADCTRL */
-			0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
-			0x0000003f, /* EMC_DSR_VTTGEN_DRV */
-			0x00000000, /* EMC_TXDSRVTTGEN */
-			0x02000000, /* EMC_FBIO_SPARE */
-			0x00000802, /* EMC_CTT_TERM_CTRL */
-			0x00000000, /* EMC_ZCAL_INTERVAL */
-			0x00000042, /* EMC_ZCAL_WAIT_CNT */
-			0x000f000f, /* EMC_MRS_WAIT_CNT */
-			0x000f000f, /* EMC_MRS_WAIT_CNT2 */
-			0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-			0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-			0x00000000, /* EMC_CTT */
-			0x00000000, /* EMC_CTT_DURATION */
-			0x800001c5, /* EMC_DYN_SELF_REF_CONTROL */
-			0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
-			0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
-			0x40040001, /* MC_EMEM_ARB_CFG */
-			0x8000003f, /* MC_EMEM_ARB_OUTSTANDING_REQ */
-			0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
-			0x00000001, /* MC_EMEM_ARB_TIMING_RP */
-			0x00000002, /* MC_EMEM_ARB_TIMING_RC */
-			0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
-			0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
-			0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
-			0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
-			0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
-			0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
-			0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
-			0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
-			0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
-			0x06030102, /* MC_EMEM_ARB_DA_TURNS */
-			0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
-			0x77e30303, /* MC_EMEM_ARB_MISC0 */
-			0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
-		},
-		{
-			0x00000000, /* EMC_CDB_CNTL_1 */
-			0x00000004, /* EMC_FBIO_CFG6 */
-			0x00000006, /* EMC_QUSE */
-			0x00000003, /* EMC_EINPUT */
-			0x00000004, /* EMC_EINPUT_DURATION */
-			0x00070000, /* EMC_DLL_XFORM_DQS0 */
-			0x0000000a, /* EMC_QSAFE */
-			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
-			0x0000000c, /* EMC_RDV */
-			0x00249249, /* EMC_XM2DQSPADCTRL4 */
-			0x20820800, /* EMC_XM2DQSPADCTRL3 */
-			0x00070000, /* EMC_DLL_XFORM_DQ0 */
-			0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
-			0x00000000, /* EMC_DLL_XFORM_ADDR0 */
-			0x00000a0a, /* EMC_XM2CLKPADCTRL2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR1 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR2 */
-			0x00070000, /* EMC_DLL_XFORM_DQS1 */
-			0x00070000, /* EMC_DLL_XFORM_DQS2 */
-			0x00070000, /* EMC_DLL_XFORM_DQS3 */
-			0x00070000, /* EMC_DLL_XFORM_DQ1 */
-			0x00070000, /* EMC_DLL_XFORM_DQ2 */
-			0x00070000, /* EMC_DLL_XFORM_DQ3 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
-		},
-		{
-			0x00000000, /* EMC_CDB_CNTL_1 */
-			0x00000004, /* EMC_FBIO_CFG6 */
-			0x00000006, /* EMC_QUSE */
-			0x00000003, /* EMC_EINPUT */
-			0x00000004, /* EMC_EINPUT_DURATION */
-			0x00070000, /* EMC_DLL_XFORM_DQS0 */
-			0x0000000a, /* EMC_QSAFE */
-			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
-			0x0000000c, /* EMC_RDV */
-			0x00249249, /* EMC_XM2DQSPADCTRL4 */
-			0x20820800, /* EMC_XM2DQSPADCTRL3 */
-			0x00070000, /* EMC_DLL_XFORM_DQ0 */
-			0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
-			0x00000000, /* EMC_DLL_XFORM_ADDR0 */
-			0x00000a0a, /* EMC_XM2CLKPADCTRL2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR1 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR2 */
-			0x00070000, /* EMC_DLL_XFORM_DQS1 */
-			0x00070000, /* EMC_DLL_XFORM_DQS2 */
-			0x00070000, /* EMC_DLL_XFORM_DQS3 */
-			0x00070000, /* EMC_DLL_XFORM_DQ1 */
-			0x00070000, /* EMC_DLL_XFORM_DQ2 */
-			0x00070000, /* EMC_DLL_XFORM_DQ3 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
-		},
-		{
-			0x0000000e, /* MC_PTSA_GRANT_DECREMENT */
-			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_0 */
-			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_1 */
-			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_0 */
-			0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_0 */
-			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_2 */
-			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_1 */
-			0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_1 */
-			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV3 */
-			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */
-			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
-		},
-		0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
-		0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
-		0x7320000e, /* EMC_CFG */
-		0x80001221, /* Mode Register 0 */
-		0x80100003, /* Mode Register 1 */
-		0x80200008, /* Mode Register 2 */
-		0x00000000, /* Mode Register 4 */
-		57820,      /* expected dvfs latency (ns) */
-	},
-	{
-		0x41,       /* Rev 4.0.3 */
-		20400,      /* SDRAM frequency */
-		900,       /* min voltage */
-		"pll_p",    /* clock source id */
-		0x40000026, /* CLK_SOURCE_EMC */
-		99,         /* number of burst_regs */
-		30,         /* number of trim_regs (each channel) */
-		11,         /* number of up_down_regs */
-		{
-			0x00000000, /* EMC_RC */
-			0x00000005, /* EMC_RFC */
-			0x00000000, /* EMC_RFC_SLR */
-			0x00000000, /* EMC_RAS */
-			0x00000000, /* EMC_RP */
-			0x00000004, /* EMC_R2W */
-			0x0000000a, /* EMC_W2R */
-			0x00000003, /* EMC_R2P */
-			0x0000000b, /* EMC_W2P */
-			0x00000000, /* EMC_RD_RCD */
-			0x00000000, /* EMC_WR_RCD */
-			0x00000003, /* EMC_RRD */
-			0x00000001, /* EMC_REXT */
-			0x00000000, /* EMC_WEXT */
-			0x00000005, /* EMC_WDV */
-			0x0000000f, /* EMC_WDV_MASK */
-			0x00000005, /* EMC_IBDLY */
-			0x00010000, /* EMC_PUTERM_EXTRA */
-			0x00000000, /* EMC_CDB_CNTL_2 */
-			0x00000004, /* EMC_QRST */
-			0x0000000e, /* EMC_RDV_MASK */
-			0x0000009a, /* EMC_REFRESH */
-			0x00000000, /* EMC_BURST_REFRESH_NUM */
-			0x00000026, /* EMC_PRE_REFRESH_REQ_CNT */
-			0x00000002, /* EMC_PDEX2WR */
-			0x00000002, /* EMC_PDEX2RD */
-			0x00000001, /* EMC_PCHG2PDEN */
-			0x00000000, /* EMC_ACT2PDEN */
-			0x00000007, /* EMC_AR2PDEN */
-			0x0000000f, /* EMC_RW2PDEN */
-			0x00000006, /* EMC_TXSR */
-			0x00000006, /* EMC_TXSRDLL */
-			0x00000004, /* EMC_TCKE */
-			0x00000004, /* EMC_TCKESR */
-			0x00000004, /* EMC_TPD */
-			0x00000004, /* EMC_TFAW */
-			0x00000000, /* EMC_TRPAB */
-			0x00000004, /* EMC_TCLKSTABLE */
-			0x00000005, /* EMC_TCLKSTOP */
-			0x000000a0, /* EMC_TREFBW */
-			0x00000005, /* EMC_QUSE_EXTRA */
-			0x00000020, /* EMC_ODT_WRITE */
-			0x00000000, /* EMC_ODT_READ */
-			0x0000aa88, /* EMC_FBIO_CFG5 */
-			0x002c00a0, /* EMC_CFG_DIG_DLL */
-			0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
-			0x00070000, /* EMC_DLL_XFORM_DQS4 */
-			0x00070000, /* EMC_DLL_XFORM_DQS5 */
-			0x00070000, /* EMC_DLL_XFORM_DQS6 */
-			0x00070000, /* EMC_DLL_XFORM_DQS7 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE4 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE5 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE6 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE7 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
-			0x001112a0, /* EMC_XM2CMDPADCTRL */
-			0x00000000, /* EMC_XM2CMDPADCTRL4 */
-			0x0000a11c, /* EMC_XM2DQSPADCTRL2 */
-			0x00000000, /* EMC_XM2DQPADCTRL2 */
-			0x77ffc085, /* EMC_XM2CLKPADCTRL */
-			0x81f1f108, /* EMC_XM2COMPPADCTRL */
-			0x03035504, /* EMC_XM2VTTGENPADCTRL */
-			0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
-			0x0000003f, /* EMC_DSR_VTTGEN_DRV */
-			0x00000000, /* EMC_TXDSRVTTGEN */
-			0x02000000, /* EMC_FBIO_SPARE */
-			0x00000802, /* EMC_CTT_TERM_CTRL */
-			0x00000000, /* EMC_ZCAL_INTERVAL */
-			0x00000042, /* EMC_ZCAL_WAIT_CNT */
-			0x000f000f, /* EMC_MRS_WAIT_CNT */
-			0x000f000f, /* EMC_MRS_WAIT_CNT2 */
-			0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-			0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-			0x00000000, /* EMC_CTT */
-			0x00000000, /* EMC_CTT_DURATION */
-			0x8000023a, /* EMC_DYN_SELF_REF_CONTROL */
-			0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
-			0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
-			0x40020001, /* MC_EMEM_ARB_CFG */
-			0x80000046, /* MC_EMEM_ARB_OUTSTANDING_REQ */
-			0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
-			0x00000001, /* MC_EMEM_ARB_TIMING_RP */
-			0x00000002, /* MC_EMEM_ARB_TIMING_RC */
-			0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
-			0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
-			0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
-			0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
-			0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
-			0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
-			0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
-			0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
-			0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
-			0x06030102, /* MC_EMEM_ARB_DA_TURNS */
-			0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
-			0x76230303, /* MC_EMEM_ARB_MISC0 */
-			0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
-		},
-		{
-			0x00000000, /* EMC_CDB_CNTL_1 */
-			0x00000004, /* EMC_FBIO_CFG6 */
-			0x00000006, /* EMC_QUSE */
-			0x00000003, /* EMC_EINPUT */
-			0x00000004, /* EMC_EINPUT_DURATION */
-			0x00070000, /* EMC_DLL_XFORM_DQS0 */
-			0x0000000a, /* EMC_QSAFE */
-			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
-			0x0000000c, /* EMC_RDV */
-			0x00249249, /* EMC_XM2DQSPADCTRL4 */
-			0x20820800, /* EMC_XM2DQSPADCTRL3 */
-			0x00070000, /* EMC_DLL_XFORM_DQ0 */
-			0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
-			0x00000000, /* EMC_DLL_XFORM_ADDR0 */
-			0x00000a0a, /* EMC_XM2CLKPADCTRL2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR1 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR2 */
-			0x00070000, /* EMC_DLL_XFORM_DQS1 */
-			0x00070000, /* EMC_DLL_XFORM_DQS2 */
-			0x00070000, /* EMC_DLL_XFORM_DQS3 */
-			0x00070000, /* EMC_DLL_XFORM_DQ1 */
-			0x00070000, /* EMC_DLL_XFORM_DQ2 */
-			0x00070000, /* EMC_DLL_XFORM_DQ3 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
-		},
-		{
-			0x00000000, /* EMC_CDB_CNTL_1 */
-			0x00000004, /* EMC_FBIO_CFG6 */
-			0x00000006, /* EMC_QUSE */
-			0x00000003, /* EMC_EINPUT */
-			0x00000004, /* EMC_EINPUT_DURATION */
-			0x00070000, /* EMC_DLL_XFORM_DQS0 */
-			0x0000000a, /* EMC_QSAFE */
-			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
-			0x0000000c, /* EMC_RDV */
-			0x00249249, /* EMC_XM2DQSPADCTRL4 */
-			0x20820800, /* EMC_XM2DQSPADCTRL3 */
-			0x00070000, /* EMC_DLL_XFORM_DQ0 */
-			0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
-			0x00000000, /* EMC_DLL_XFORM_ADDR0 */
-			0x00000a0a, /* EMC_XM2CLKPADCTRL2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR1 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR2 */
-			0x00070000, /* EMC_DLL_XFORM_DQS1 */
-			0x00070000, /* EMC_DLL_XFORM_DQS2 */
-			0x00070000, /* EMC_DLL_XFORM_DQS3 */
-			0x00070000, /* EMC_DLL_XFORM_DQ1 */
-			0x00070000, /* EMC_DLL_XFORM_DQ2 */
-			0x00070000, /* EMC_DLL_XFORM_DQ3 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
-		},
-		{
-			0x00000014, /* MC_PTSA_GRANT_DECREMENT */
-			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_0 */
-			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_1 */
-			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_0 */
-			0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_0 */
-			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_2 */
-			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_1 */
-			0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_1 */
-			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV3 */
-			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */
-			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
-		},
-		0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
-		0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
-		0x7320000e, /* EMC_CFG */
-		0x80001221, /* Mode Register 0 */
-		0x80100003, /* Mode Register 1 */
-		0x80200008, /* Mode Register 2 */
-		0x00000000, /* Mode Register 4 */
-		35610,      /* expected dvfs latency (ns) */
-	},
-	{
-		0x41,       /* Rev 4.0.3 */
-		40800,      /* SDRAM frequency */
-		900,       /* min voltage */
-		"pll_p",    /* clock source id */
-		0x40000012, /* CLK_SOURCE_EMC */
-		99,         /* number of burst_regs */
-		30,         /* number of trim_regs (each channel) */
-		11,         /* number of up_down_regs */
-		{
-			0x00000001, /* EMC_RC */
-			0x0000000a, /* EMC_RFC */
-			0x00000000, /* EMC_RFC_SLR */
-			0x00000001, /* EMC_RAS */
-			0x00000000, /* EMC_RP */
-			0x00000004, /* EMC_R2W */
-			0x0000000a, /* EMC_W2R */
-			0x00000003, /* EMC_R2P */
-			0x0000000b, /* EMC_W2P */
-			0x00000000, /* EMC_RD_RCD */
-			0x00000000, /* EMC_WR_RCD */
-			0x00000003, /* EMC_RRD */
-			0x00000001, /* EMC_REXT */
-			0x00000000, /* EMC_WEXT */
-			0x00000005, /* EMC_WDV */
-			0x0000000f, /* EMC_WDV_MASK */
-			0x00000005, /* EMC_IBDLY */
-			0x00010000, /* EMC_PUTERM_EXTRA */
-			0x00000000, /* EMC_CDB_CNTL_2 */
-			0x00000004, /* EMC_QRST */
-			0x0000000e, /* EMC_RDV_MASK */
-			0x00000134, /* EMC_REFRESH */
-			0x00000000, /* EMC_BURST_REFRESH_NUM */
-			0x0000004d, /* EMC_PRE_REFRESH_REQ_CNT */
-			0x00000002, /* EMC_PDEX2WR */
-			0x00000002, /* EMC_PDEX2RD */
-			0x00000001, /* EMC_PCHG2PDEN */
-			0x00000000, /* EMC_ACT2PDEN */
-			0x00000008, /* EMC_AR2PDEN */
-			0x0000000f, /* EMC_RW2PDEN */
-			0x0000000c, /* EMC_TXSR */
-			0x0000000c, /* EMC_TXSRDLL */
-			0x00000004, /* EMC_TCKE */
-			0x00000004, /* EMC_TCKESR */
-			0x00000004, /* EMC_TPD */
-			0x00000004, /* EMC_TFAW */
-			0x00000000, /* EMC_TRPAB */
-			0x00000004, /* EMC_TCLKSTABLE */
-			0x00000005, /* EMC_TCLKSTOP */
-			0x0000013f, /* EMC_TREFBW */
-			0x00000005, /* EMC_QUSE_EXTRA */
-			0x00000020, /* EMC_ODT_WRITE */
-			0x00000000, /* EMC_ODT_READ */
-			0x0000aa88, /* EMC_FBIO_CFG5 */
-			0x002c00a0, /* EMC_CFG_DIG_DLL */
-			0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
-			0x00070000, /* EMC_DLL_XFORM_DQS4 */
-			0x00070000, /* EMC_DLL_XFORM_DQS5 */
-			0x00070000, /* EMC_DLL_XFORM_DQS6 */
-			0x00070000, /* EMC_DLL_XFORM_DQS7 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE4 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE5 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE6 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE7 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
-			0x001112a0, /* EMC_XM2CMDPADCTRL */
-			0x00000000, /* EMC_XM2CMDPADCTRL4 */
-			0x0000a11c, /* EMC_XM2DQSPADCTRL2 */
-			0x00000000, /* EMC_XM2DQPADCTRL2 */
-			0x77ffc085, /* EMC_XM2CLKPADCTRL */
-			0x81f1f108, /* EMC_XM2COMPPADCTRL */
-			0x03035504, /* EMC_XM2VTTGENPADCTRL */
-			0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
-			0x0000003f, /* EMC_DSR_VTTGEN_DRV */
-			0x00000000, /* EMC_TXDSRVTTGEN */
-			0x02000000, /* EMC_FBIO_SPARE */
-			0x00000802, /* EMC_CTT_TERM_CTRL */
-			0x00000000, /* EMC_ZCAL_INTERVAL */
-			0x00000042, /* EMC_ZCAL_WAIT_CNT */
-			0x000f000f, /* EMC_MRS_WAIT_CNT */
-			0x000f000f, /* EMC_MRS_WAIT_CNT2 */
-			0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-			0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-			0x00000000, /* EMC_CTT */
-			0x00000000, /* EMC_CTT_DURATION */
-			0x80000370, /* EMC_DYN_SELF_REF_CONTROL */
-			0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
-			0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
-			0xa0000001, /* MC_EMEM_ARB_CFG */
-			0x8000005b, /* MC_EMEM_ARB_OUTSTANDING_REQ */
-			0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
-			0x00000001, /* MC_EMEM_ARB_TIMING_RP */
-			0x00000002, /* MC_EMEM_ARB_TIMING_RC */
-			0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
-			0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
-			0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
-			0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
-			0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
-			0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
-			0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
-			0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
-			0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
-			0x06030102, /* MC_EMEM_ARB_DA_TURNS */
-			0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
-			0x74a30303, /* MC_EMEM_ARB_MISC0 */
-			0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
-		},
-		{
-			0x00000000, /* EMC_CDB_CNTL_1 */
-			0x00000004, /* EMC_FBIO_CFG6 */
-			0x00000006, /* EMC_QUSE */
-			0x00000003, /* EMC_EINPUT */
-			0x00000004, /* EMC_EINPUT_DURATION */
-			0x00070000, /* EMC_DLL_XFORM_DQS0 */
-			0x0000000a, /* EMC_QSAFE */
-			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
-			0x0000000c, /* EMC_RDV */
-			0x00249249, /* EMC_XM2DQSPADCTRL4 */
-			0x20820800, /* EMC_XM2DQSPADCTRL3 */
-			0x00070000, /* EMC_DLL_XFORM_DQ0 */
-			0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
-			0x00000000, /* EMC_DLL_XFORM_ADDR0 */
-			0x00000a0a, /* EMC_XM2CLKPADCTRL2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR1 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR2 */
-			0x00070000, /* EMC_DLL_XFORM_DQS1 */
-			0x00070000, /* EMC_DLL_XFORM_DQS2 */
-			0x00070000, /* EMC_DLL_XFORM_DQS3 */
-			0x00070000, /* EMC_DLL_XFORM_DQ1 */
-			0x00070000, /* EMC_DLL_XFORM_DQ2 */
-			0x00070000, /* EMC_DLL_XFORM_DQ3 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
-		},
-		{
-			0x00000000, /* EMC_CDB_CNTL_1 */
-			0x00000004, /* EMC_FBIO_CFG6 */
-			0x00000006, /* EMC_QUSE */
-			0x00000003, /* EMC_EINPUT */
-			0x00000004, /* EMC_EINPUT_DURATION */
-			0x00070000, /* EMC_DLL_XFORM_DQS0 */
-			0x0000000a, /* EMC_QSAFE */
-			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
-			0x0000000c, /* EMC_RDV */
-			0x00249249, /* EMC_XM2DQSPADCTRL4 */
-			0x20820800, /* EMC_XM2DQSPADCTRL3 */
-			0x00070000, /* EMC_DLL_XFORM_DQ0 */
-			0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
-			0x00000000, /* EMC_DLL_XFORM_ADDR0 */
-			0x00000a0a, /* EMC_XM2CLKPADCTRL2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR1 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR2 */
-			0x00070000, /* EMC_DLL_XFORM_DQS1 */
-			0x00070000, /* EMC_DLL_XFORM_DQS2 */
-			0x00070000, /* EMC_DLL_XFORM_DQS3 */
-			0x00070000, /* EMC_DLL_XFORM_DQ1 */
-			0x00070000, /* EMC_DLL_XFORM_DQ2 */
-			0x00070000, /* EMC_DLL_XFORM_DQ3 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
-		},
-		{
-			0x0000002a, /* MC_PTSA_GRANT_DECREMENT */
-			0x00b000b0, /* MC_LATENCY_ALLOWANCE_G2_0 */
-			0x00b000c4, /* MC_LATENCY_ALLOWANCE_G2_1 */
-			0x00d700eb, /* MC_LATENCY_ALLOWANCE_NV_0 */
-			0x000000eb, /* MC_LATENCY_ALLOWANCE_NV2_0 */
-			0x00eb00eb, /* MC_LATENCY_ALLOWANCE_NV_2 */
-			0x00ff00eb, /* MC_LATENCY_ALLOWANCE_NV_1 */
-			0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_1 */
-			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV3 */
-			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */
-			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
-		},
-		0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
-		0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
-		0x7320000e, /* EMC_CFG */
-		0x80001221, /* Mode Register 0 */
-		0x80100003, /* Mode Register 1 */
-		0x80200008, /* Mode Register 2 */
-		0x00000000, /* Mode Register 4 */
-		20850,      /* expected dvfs latency (ns) */
-	},
-	{
-		0x41,       /* Rev 4.0.3 */
-		68000,      /* SDRAM frequency */
-		900,       /* min voltage */
-		"pll_p",    /* clock source id */
-		0x4000000a, /* CLK_SOURCE_EMC */
-		99,         /* number of burst_regs */
-		30,         /* number of trim_regs (each channel) */
-		11,         /* number of up_down_regs */
-		{
-			0x00000003, /* EMC_RC */
-			0x00000011, /* EMC_RFC */
-			0x00000000, /* EMC_RFC_SLR */
-			0x00000002, /* EMC_RAS */
-			0x00000000, /* EMC_RP */
-			0x00000004, /* EMC_R2W */
-			0x0000000a, /* EMC_W2R */
-			0x00000003, /* EMC_R2P */
-			0x0000000b, /* EMC_W2P */
-			0x00000000, /* EMC_RD_RCD */
-			0x00000000, /* EMC_WR_RCD */
-			0x00000003, /* EMC_RRD */
-			0x00000001, /* EMC_REXT */
-			0x00000000, /* EMC_WEXT */
-			0x00000005, /* EMC_WDV */
-			0x0000000f, /* EMC_WDV_MASK */
-			0x00000005, /* EMC_IBDLY */
-			0x00010000, /* EMC_PUTERM_EXTRA */
-			0x00000000, /* EMC_CDB_CNTL_2 */
-			0x00000004, /* EMC_QRST */
-			0x0000000e, /* EMC_RDV_MASK */
-			0x00000202, /* EMC_REFRESH */
-			0x00000000, /* EMC_BURST_REFRESH_NUM */
-			0x00000080, /* EMC_PRE_REFRESH_REQ_CNT */
-			0x00000002, /* EMC_PDEX2WR */
-			0x00000002, /* EMC_PDEX2RD */
-			0x00000001, /* EMC_PCHG2PDEN */
-			0x00000000, /* EMC_ACT2PDEN */
-			0x0000000f, /* EMC_AR2PDEN */
-			0x0000000f, /* EMC_RW2PDEN */
-			0x00000013, /* EMC_TXSR */
-			0x00000013, /* EMC_TXSRDLL */
-			0x00000004, /* EMC_TCKE */
-			0x00000004, /* EMC_TCKESR */
-			0x00000004, /* EMC_TPD */
-			0x00000004, /* EMC_TFAW */
-			0x00000000, /* EMC_TRPAB */
-			0x00000004, /* EMC_TCLKSTABLE */
-			0x00000005, /* EMC_TCLKSTOP */
-			0x00000213, /* EMC_TREFBW */
-			0x00000005, /* EMC_QUSE_EXTRA */
-			0x00000020, /* EMC_ODT_WRITE */
-			0x00000000, /* EMC_ODT_READ */
-			0x0000aa88, /* EMC_FBIO_CFG5 */
-			0x002c00a0, /* EMC_CFG_DIG_DLL */
-			0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
-			0x00070000, /* EMC_DLL_XFORM_DQS4 */
-			0x00070000, /* EMC_DLL_XFORM_DQS5 */
-			0x00070000, /* EMC_DLL_XFORM_DQS6 */
-			0x00070000, /* EMC_DLL_XFORM_DQS7 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE4 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE5 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE6 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE7 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
-			0x001112a0, /* EMC_XM2CMDPADCTRL */
-			0x00000000, /* EMC_XM2CMDPADCTRL4 */
-			0x0000a11c, /* EMC_XM2DQSPADCTRL2 */
-			0x00000000, /* EMC_XM2DQPADCTRL2 */
-			0x77ffc085, /* EMC_XM2CLKPADCTRL */
-			0x81f1f108, /* EMC_XM2COMPPADCTRL */
-			0x03035504, /* EMC_XM2VTTGENPADCTRL */
-			0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
-			0x0000003f, /* EMC_DSR_VTTGEN_DRV */
-			0x00000000, /* EMC_TXDSRVTTGEN */
-			0x02000000, /* EMC_FBIO_SPARE */
-			0x00000802, /* EMC_CTT_TERM_CTRL */
-			0x00000000, /* EMC_ZCAL_INTERVAL */
-			0x00000042, /* EMC_ZCAL_WAIT_CNT */
-			0x000f000f, /* EMC_MRS_WAIT_CNT */
-			0x000f000f, /* EMC_MRS_WAIT_CNT2 */
-			0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-			0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-			0x00000000, /* EMC_CTT */
-			0x00000000, /* EMC_CTT_DURATION */
-			0x8000050d, /* EMC_DYN_SELF_REF_CONTROL */
-			0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
-			0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
-			0x00000001, /* MC_EMEM_ARB_CFG */
-			0x80000076, /* MC_EMEM_ARB_OUTSTANDING_REQ */
-			0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
-			0x00000001, /* MC_EMEM_ARB_TIMING_RP */
-			0x00000002, /* MC_EMEM_ARB_TIMING_RC */
-			0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
-			0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
-			0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
-			0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
-			0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
-			0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
-			0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
-			0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
-			0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
-			0x06030102, /* MC_EMEM_ARB_DA_TURNS */
-			0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
-			0x74230403, /* MC_EMEM_ARB_MISC0 */
-			0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
-		},
-		{
-			0x00000000, /* EMC_CDB_CNTL_1 */
-			0x00000004, /* EMC_FBIO_CFG6 */
-			0x00000006, /* EMC_QUSE */
-			0x00000003, /* EMC_EINPUT */
-			0x00000004, /* EMC_EINPUT_DURATION */
-			0x00070000, /* EMC_DLL_XFORM_DQS0 */
-			0x0000000a, /* EMC_QSAFE */
-			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
-			0x0000000c, /* EMC_RDV */
-			0x00249249, /* EMC_XM2DQSPADCTRL4 */
-			0x20820800, /* EMC_XM2DQSPADCTRL3 */
-			0x00070000, /* EMC_DLL_XFORM_DQ0 */
-			0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
-			0x00000000, /* EMC_DLL_XFORM_ADDR0 */
-			0x00001e1e, /* EMC_XM2CLKPADCTRL2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR1 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR2 */
-			0x00070000, /* EMC_DLL_XFORM_DQS1 */
-			0x00070000, /* EMC_DLL_XFORM_DQS2 */
-			0x00070000, /* EMC_DLL_XFORM_DQS3 */
-			0x00070000, /* EMC_DLL_XFORM_DQ1 */
-			0x00070000, /* EMC_DLL_XFORM_DQ2 */
-			0x00070000, /* EMC_DLL_XFORM_DQ3 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
-		},
-		{
-			0x00000000, /* EMC_CDB_CNTL_1 */
-			0x00000004, /* EMC_FBIO_CFG6 */
-			0x00000006, /* EMC_QUSE */
-			0x00000003, /* EMC_EINPUT */
-			0x00000004, /* EMC_EINPUT_DURATION */
-			0x00070000, /* EMC_DLL_XFORM_DQS0 */
-			0x0000000a, /* EMC_QSAFE */
-			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
-			0x0000000c, /* EMC_RDV */
-			0x00249249, /* EMC_XM2DQSPADCTRL4 */
-			0x20820800, /* EMC_XM2DQSPADCTRL3 */
-			0x00070000, /* EMC_DLL_XFORM_DQ0 */
-			0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
-			0x00000000, /* EMC_DLL_XFORM_ADDR0 */
-			0x00001e1e, /* EMC_XM2CLKPADCTRL2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR1 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR2 */
-			0x00070000, /* EMC_DLL_XFORM_DQS1 */
-			0x00070000, /* EMC_DLL_XFORM_DQS2 */
-			0x00070000, /* EMC_DLL_XFORM_DQS3 */
-			0x00070000, /* EMC_DLL_XFORM_DQ1 */
-			0x00070000, /* EMC_DLL_XFORM_DQ2 */
-			0x00070000, /* EMC_DLL_XFORM_DQ3 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
-		},
-		{
-			0x00000046, /* MC_PTSA_GRANT_DECREMENT */
-			0x00690069, /* MC_LATENCY_ALLOWANCE_G2_0 */
-			0x00690075, /* MC_LATENCY_ALLOWANCE_G2_1 */
-			0x0081008d, /* MC_LATENCY_ALLOWANCE_NV_0 */
-			0x0000008d, /* MC_LATENCY_ALLOWANCE_NV2_0 */
-			0x008d008d, /* MC_LATENCY_ALLOWANCE_NV_2 */
-			0x00bc008d, /* MC_LATENCY_ALLOWANCE_NV_1 */
-			0x000000bc, /* MC_LATENCY_ALLOWANCE_NV2_1 */
-			0x00bc00bc, /* MC_LATENCY_ALLOWANCE_NV3 */
-			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */
-			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
-		},
-		0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
-		0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
-		0x7320000e, /* EMC_CFG */
-		0x80001221, /* Mode Register 0 */
-		0x80100003, /* Mode Register 1 */
-		0x80200008, /* Mode Register 2 */
-		0x00000000, /* Mode Register 4 */
-		10720,      /* expected dvfs latency (ns) */
-	},
-	{
-		0x41,       /* Rev 4.0.3 */
-		102000,     /* SDRAM frequency */
-		900,       /* min voltage */
-		"pll_p",    /* clock source id */
-		0x40000006, /* CLK_SOURCE_EMC */
-		99,         /* number of burst_regs */
-		30,         /* number of trim_regs (each channel) */
-		11,         /* number of up_down_regs */
-		{
-			0x00000004, /* EMC_RC */
-			0x0000001a, /* EMC_RFC */
-			0x00000000, /* EMC_RFC_SLR */
-			0x00000003, /* EMC_RAS */
-			0x00000001, /* EMC_RP */
-			0x00000004, /* EMC_R2W */
-			0x0000000a, /* EMC_W2R */
-			0x00000003, /* EMC_R2P */
-			0x0000000b, /* EMC_W2P */
-			0x00000001, /* EMC_RD_RCD */
-			0x00000001, /* EMC_WR_RCD */
-			0x00000003, /* EMC_RRD */
-			0x00000001, /* EMC_REXT */
-			0x00000000, /* EMC_WEXT */
-			0x00000005, /* EMC_WDV */
-			0x0000000f, /* EMC_WDV_MASK */
-			0x00000005, /* EMC_IBDLY */
-			0x00010000, /* EMC_PUTERM_EXTRA */
-			0x00000000, /* EMC_CDB_CNTL_2 */
-			0x00000004, /* EMC_QRST */
-			0x0000000e, /* EMC_RDV_MASK */
-			0x00000303, /* EMC_REFRESH */
-			0x00000000, /* EMC_BURST_REFRESH_NUM */
-			0x000000c0, /* EMC_PRE_REFRESH_REQ_CNT */
-			0x00000002, /* EMC_PDEX2WR */
-			0x00000002, /* EMC_PDEX2RD */
-			0x00000001, /* EMC_PCHG2PDEN */
-			0x00000000, /* EMC_ACT2PDEN */
-			0x00000018, /* EMC_AR2PDEN */
-			0x0000000f, /* EMC_RW2PDEN */
-			0x0000001c, /* EMC_TXSR */
-			0x0000001c, /* EMC_TXSRDLL */
-			0x00000004, /* EMC_TCKE */
-			0x00000004, /* EMC_TCKESR */
-			0x00000004, /* EMC_TPD */
-			0x00000005, /* EMC_TFAW */
-			0x00000000, /* EMC_TRPAB */
-			0x00000004, /* EMC_TCLKSTABLE */
-			0x00000005, /* EMC_TCLKSTOP */
-			0x0000031c, /* EMC_TREFBW */
-			0x00000005, /* EMC_QUSE_EXTRA */
-			0x00000020, /* EMC_ODT_WRITE */
-			0x00000000, /* EMC_ODT_READ */
-			0x0000aa88, /* EMC_FBIO_CFG5 */
-			0x002c00a0, /* EMC_CFG_DIG_DLL */
-			0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
-			0x00070000, /* EMC_DLL_XFORM_DQS4 */
-			0x00070000, /* EMC_DLL_XFORM_DQS5 */
-			0x00070000, /* EMC_DLL_XFORM_DQS6 */
-			0x00070000, /* EMC_DLL_XFORM_DQS7 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE4 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE5 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE6 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE7 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
-			0x001112a0, /* EMC_XM2CMDPADCTRL */
-			0x00000000, /* EMC_XM2CMDPADCTRL4 */
-			0x0000a11c, /* EMC_XM2DQSPADCTRL2 */
-			0x00000000, /* EMC_XM2DQPADCTRL2 */
-			0x77ffc085, /* EMC_XM2CLKPADCTRL */
-			0x81f1f108, /* EMC_XM2COMPPADCTRL */
-			0x03035504, /* EMC_XM2VTTGENPADCTRL */
-			0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
-			0x0000003f, /* EMC_DSR_VTTGEN_DRV */
-			0x00000000, /* EMC_TXDSRVTTGEN */
-			0x02000000, /* EMC_FBIO_SPARE */
-			0x00000802, /* EMC_CTT_TERM_CTRL */
-			0x00000000, /* EMC_ZCAL_INTERVAL */
-			0x00000042, /* EMC_ZCAL_WAIT_CNT */
-			0x000f000f, /* EMC_MRS_WAIT_CNT */
-			0x000f000f, /* EMC_MRS_WAIT_CNT2 */
-			0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-			0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-			0x00000000, /* EMC_CTT */
-			0x00000000, /* EMC_CTT_DURATION */
-			0x80000714, /* EMC_DYN_SELF_REF_CONTROL */
-			0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
-			0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
-			0x08000001, /* MC_EMEM_ARB_CFG */
-			0x80000098, /* MC_EMEM_ARB_OUTSTANDING_REQ */
-			0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
-			0x00000001, /* MC_EMEM_ARB_TIMING_RP */
-			0x00000003, /* MC_EMEM_ARB_TIMING_RC */
-			0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
-			0x00000002, /* MC_EMEM_ARB_TIMING_FAW */
-			0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
-			0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
-			0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
-			0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
-			0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
-			0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
-			0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
-			0x06030102, /* MC_EMEM_ARB_DA_TURNS */
-			0x000a0403, /* MC_EMEM_ARB_DA_COVERS */
-			0x73c30504, /* MC_EMEM_ARB_MISC0 */
-			0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
-		},
-		{
-			0x00000000, /* EMC_CDB_CNTL_1 */
-			0x00000006, /* EMC_FBIO_CFG6 */
-			0x00000006, /* EMC_QUSE */
-			0x00000005, /* EMC_EINPUT */
-			0x00000004, /* EMC_EINPUT_DURATION */
-			0x00070000, /* EMC_DLL_XFORM_DQS0 */
-			0x0000000a, /* EMC_QSAFE */
-			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
-			0x0000000c, /* EMC_RDV */
-			0x00249249, /* EMC_XM2DQSPADCTRL4 */
-			0x20820800, /* EMC_XM2DQSPADCTRL3 */
-			0x00070000, /* EMC_DLL_XFORM_DQ0 */
-			0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
-			0x00000000, /* EMC_DLL_XFORM_ADDR0 */
-			0x00000a0a, /* EMC_XM2CLKPADCTRL2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR1 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR2 */
-			0x00070000, /* EMC_DLL_XFORM_DQS1 */
-			0x00070000, /* EMC_DLL_XFORM_DQS2 */
-			0x00070000, /* EMC_DLL_XFORM_DQS3 */
-			0x00070000, /* EMC_DLL_XFORM_DQ1 */
-			0x00070000, /* EMC_DLL_XFORM_DQ2 */
-			0x00070000, /* EMC_DLL_XFORM_DQ3 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
-		},
-		{
-			0x00000000, /* EMC_CDB_CNTL_1 */
-			0x00000006, /* EMC_FBIO_CFG6 */
-			0x00000006, /* EMC_QUSE */
-			0x00000005, /* EMC_EINPUT */
-			0x00000004, /* EMC_EINPUT_DURATION */
-			0x00070000, /* EMC_DLL_XFORM_DQS0 */
-			0x0000000a, /* EMC_QSAFE */
-			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
-			0x0000000c, /* EMC_RDV */
-			0x00249249, /* EMC_XM2DQSPADCTRL4 */
-			0x20820800, /* EMC_XM2DQSPADCTRL3 */
-			0x00070000, /* EMC_DLL_XFORM_DQ0 */
-			0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
-			0x00000000, /* EMC_DLL_XFORM_ADDR0 */
-			0x00000a0a, /* EMC_XM2CLKPADCTRL2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR1 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR2 */
-			0x00070000, /* EMC_DLL_XFORM_DQS1 */
-			0x00070000, /* EMC_DLL_XFORM_DQS2 */
-			0x00070000, /* EMC_DLL_XFORM_DQS3 */
-			0x00070000, /* EMC_DLL_XFORM_DQ1 */
-			0x00070000, /* EMC_DLL_XFORM_DQ2 */
-			0x00070000, /* EMC_DLL_XFORM_DQ3 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
-		},
-		{
-			0x00000068, /* MC_PTSA_GRANT_DECREMENT */
-			0x00460046, /* MC_LATENCY_ALLOWANCE_G2_0 */
-			0x0046004e, /* MC_LATENCY_ALLOWANCE_G2_1 */
-			0x0056005e, /* MC_LATENCY_ALLOWANCE_NV_0 */
-			0x0000005e, /* MC_LATENCY_ALLOWANCE_NV2_0 */
-			0x005e005e, /* MC_LATENCY_ALLOWANCE_NV_2 */
-			0x007d005e, /* MC_LATENCY_ALLOWANCE_NV_1 */
-			0x0000007d, /* MC_LATENCY_ALLOWANCE_NV2_1 */
-			0x007d007d, /* MC_LATENCY_ALLOWANCE_NV3 */
-			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */
-			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
-		},
-		0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
-		0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
-		0x7320000e, /* EMC_CFG */
-		0x80001221, /* Mode Register 0 */
-		0x80100003, /* Mode Register 1 */
-		0x80200008, /* Mode Register 2 */
-		0x00000000, /* Mode Register 4 */
-		6890,       /* expected dvfs latency (ns) */
-	},
-	{
-		0x41,       /* Rev 4.0.3 */
-		204000,     /* SDRAM frequency */
-		900,       /* min voltage */
-		"pll_p",    /* clock source id */
-		0x40000002, /* CLK_SOURCE_EMC */
-		99,         /* number of burst_regs */
-		30,         /* number of trim_regs (each channel) */
-		11,         /* number of up_down_regs */
-		{
-			0x00000009, /* EMC_RC */
-			0x00000035, /* EMC_RFC */
-			0x00000000, /* EMC_RFC_SLR */
-			0x00000006, /* EMC_RAS */
-			0x00000002, /* EMC_RP */
-			0x00000004, /* EMC_R2W */
-			0x0000000a, /* EMC_W2R */
-			0x00000003, /* EMC_R2P */
-			0x0000000b, /* EMC_W2P */
-			0x00000002, /* EMC_RD_RCD */
-			0x00000002, /* EMC_WR_RCD */
-			0x00000003, /* EMC_RRD */
-			0x00000001, /* EMC_REXT */
-			0x00000000, /* EMC_WEXT */
-			0x00000005, /* EMC_WDV */
-			0x0000000f, /* EMC_WDV_MASK */
-			0x00000006, /* EMC_IBDLY */
-			0x00010000, /* EMC_PUTERM_EXTRA */
-			0x00000000, /* EMC_CDB_CNTL_2 */
-			0x00000004, /* EMC_QRST */
-			0x0000000e, /* EMC_RDV_MASK */
-			0x00000607, /* EMC_REFRESH */
-			0x00000000, /* EMC_BURST_REFRESH_NUM */
-			0x00000181, /* EMC_PRE_REFRESH_REQ_CNT */
-			0x00000002, /* EMC_PDEX2WR */
-			0x00000002, /* EMC_PDEX2RD */
-			0x00000001, /* EMC_PCHG2PDEN */
-			0x00000000, /* EMC_ACT2PDEN */
-			0x00000032, /* EMC_AR2PDEN */
-			0x0000000f, /* EMC_RW2PDEN */
-			0x00000038, /* EMC_TXSR */
-			0x00000038, /* EMC_TXSRDLL */
-			0x00000004, /* EMC_TCKE */
-			0x00000004, /* EMC_TCKESR */
-			0x00000004, /* EMC_TPD */
-			0x00000009, /* EMC_TFAW */
-			0x00000000, /* EMC_TRPAB */
-			0x00000004, /* EMC_TCLKSTABLE */
-			0x00000005, /* EMC_TCLKSTOP */
-			0x00000638, /* EMC_TREFBW */
-			0x00000006, /* EMC_QUSE_EXTRA */
-			0x00000020, /* EMC_ODT_WRITE */
-			0x00000000, /* EMC_ODT_READ */
-			0x0000aa88, /* EMC_FBIO_CFG5 */
-			0x002c00a0, /* EMC_CFG_DIG_DLL */
-			0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
-			0x00064000, /* EMC_DLL_XFORM_DQS4 */
-			0x00064000, /* EMC_DLL_XFORM_DQS5 */
-			0x00064000, /* EMC_DLL_XFORM_DQS6 */
-			0x00064000, /* EMC_DLL_XFORM_DQS7 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE4 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE5 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE6 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE7 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
-			0x001112a0, /* EMC_XM2CMDPADCTRL */
-			0x00000000, /* EMC_XM2CMDPADCTRL4 */
-			0x0000a11c, /* EMC_XM2DQSPADCTRL2 */
-			0x00000000, /* EMC_XM2DQPADCTRL2 */
-			0x77ffc085, /* EMC_XM2CLKPADCTRL */
-			0x81f1f108, /* EMC_XM2COMPPADCTRL */
-			0x05057404, /* EMC_XM2VTTGENPADCTRL */
-			0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
-			0x0000003f, /* EMC_DSR_VTTGEN_DRV */
-			0x00000000, /* EMC_TXDSRVTTGEN */
-			0x02000000, /* EMC_FBIO_SPARE */
-			0x00000802, /* EMC_CTT_TERM_CTRL */
-			0x00020000, /* EMC_ZCAL_INTERVAL */
-			0x00000100, /* EMC_ZCAL_WAIT_CNT */
-			0x000f000f, /* EMC_MRS_WAIT_CNT */
-			0x000f000f, /* EMC_MRS_WAIT_CNT2 */
-			0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-			0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-			0x00000000, /* EMC_CTT */
-			0x00000000, /* EMC_CTT_DURATION */
-			0x80000d24, /* EMC_DYN_SELF_REF_CONTROL */
-			0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
-			0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
-			0x01000003, /* MC_EMEM_ARB_CFG */
-			0x800000fe, /* MC_EMEM_ARB_OUTSTANDING_REQ */
-			0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
-			0x00000001, /* MC_EMEM_ARB_TIMING_RP */
-			0x00000004, /* MC_EMEM_ARB_TIMING_RC */
-			0x00000002, /* MC_EMEM_ARB_TIMING_RAS */
-			0x00000004, /* MC_EMEM_ARB_TIMING_FAW */
-			0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
-			0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
-			0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
-			0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
-			0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
-			0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
-			0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
-			0x06030102, /* MC_EMEM_ARB_DA_TURNS */
-			0x000a0404, /* MC_EMEM_ARB_DA_COVERS */
-			0x73840a05, /* MC_EMEM_ARB_MISC0 */
-			0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
-		},
-		{
-			0x00000000, /* EMC_CDB_CNTL_1 */
-			0x00000004, /* EMC_FBIO_CFG6 */
-			0x00000007, /* EMC_QUSE */
-			0x00000005, /* EMC_EINPUT */
-			0x00000005, /* EMC_EINPUT_DURATION */
-			0x00064000, /* EMC_DLL_XFORM_DQS0 */
-			0x0000000a, /* EMC_QSAFE */
-			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
-			0x0000000d, /* EMC_RDV */
-			0x00249249, /* EMC_XM2DQSPADCTRL4 */
-			0x20820800, /* EMC_XM2DQSPADCTRL3 */
-			0x00070000, /* EMC_DLL_XFORM_DQ0 */
-			0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
-			0x00000000, /* EMC_DLL_XFORM_ADDR0 */
-			0x00000a0a, /* EMC_XM2CLKPADCTRL2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR1 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR2 */
-			0x00064000, /* EMC_DLL_XFORM_DQS1 */
-			0x00064000, /* EMC_DLL_XFORM_DQS2 */
-			0x00064000, /* EMC_DLL_XFORM_DQS3 */
-			0x00070000, /* EMC_DLL_XFORM_DQ1 */
-			0x00070000, /* EMC_DLL_XFORM_DQ2 */
-			0x00070000, /* EMC_DLL_XFORM_DQ3 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
-		},
-		{
-			0x00000000, /* EMC_CDB_CNTL_1 */
-			0x00000004, /* EMC_FBIO_CFG6 */
-			0x00000007, /* EMC_QUSE */
-			0x00000005, /* EMC_EINPUT */
-			0x00000005, /* EMC_EINPUT_DURATION */
-			0x00064000, /* EMC_DLL_XFORM_DQS0 */
-			0x0000000a, /* EMC_QSAFE */
-			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
-			0x0000000d, /* EMC_RDV */
-			0x00249249, /* EMC_XM2DQSPADCTRL4 */
-			0x20820800, /* EMC_XM2DQSPADCTRL3 */
-			0x00070000, /* EMC_DLL_XFORM_DQ0 */
-			0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
-			0x00000000, /* EMC_DLL_XFORM_ADDR0 */
-			0x00000a0a, /* EMC_XM2CLKPADCTRL2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR1 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR2 */
-			0x00064000, /* EMC_DLL_XFORM_DQS1 */
-			0x00064000, /* EMC_DLL_XFORM_DQS2 */
-			0x00064000, /* EMC_DLL_XFORM_DQS3 */
-			0x00070000, /* EMC_DLL_XFORM_DQ1 */
-			0x00070000, /* EMC_DLL_XFORM_DQ2 */
-			0x00070000, /* EMC_DLL_XFORM_DQ3 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
-		},
-		{
-			0x000000d0, /* MC_PTSA_GRANT_DECREMENT */
-			0x00230023, /* MC_LATENCY_ALLOWANCE_G2_0 */
-			0x00230027, /* MC_LATENCY_ALLOWANCE_G2_1 */
-			0x002b002f, /* MC_LATENCY_ALLOWANCE_NV_0 */
-			0x0000002f, /* MC_LATENCY_ALLOWANCE_NV2_0 */
-			0x002f002f, /* MC_LATENCY_ALLOWANCE_NV_2 */
-			0x003e002f, /* MC_LATENCY_ALLOWANCE_NV_1 */
-			0x0000003e, /* MC_LATENCY_ALLOWANCE_NV2_1 */
-			0x003e003e, /* MC_LATENCY_ALLOWANCE_NV3 */
-			0x00ff00c8, /* MC_LATENCY_ALLOWANCE_EPP_0 */
-			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
-		},
-		0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
-		0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
-		0x7320000e, /* EMC_CFG */
-		0x80001221, /* Mode Register 0 */
-		0x80100003, /* Mode Register 1 */
-		0x80200008, /* Mode Register 2 */
-		0x00000000, /* Mode Register 4 */
-		3420,       /* expected dvfs latency (ns) */
-	},
-	{
-		0x41,       /* Rev 4.0.3 */
-		312000,     /* SDRAM frequency */
-		1000,       /* min voltage */
-		"pll_c",    /* clock source id */
-		0x24000002, /* CLK_SOURCE_EMC */
-		99,         /* number of burst_regs */
-		30,         /* number of trim_regs (each channel) */
-		11,         /* number of up_down_regs */
-		{
-			0x0000000d, /* EMC_RC */
-			0x00000050, /* EMC_RFC */
-			0x00000000, /* EMC_RFC_SLR */
-			0x00000009, /* EMC_RAS */
-			0x00000003, /* EMC_RP */
-			0x00000004, /* EMC_R2W */
-			0x00000008, /* EMC_W2R */
-			0x00000002, /* EMC_R2P */
-			0x00000009, /* EMC_W2P */
-			0x00000003, /* EMC_RD_RCD */
-			0x00000003, /* EMC_WR_RCD */
-			0x00000002, /* EMC_RRD */
-			0x00000001, /* EMC_REXT */
-			0x00000000, /* EMC_WEXT */
-			0x00000004, /* EMC_WDV */
-			0x0000000f, /* EMC_WDV_MASK */
-			0x00000007, /* EMC_IBDLY */
-			0x00010000, /* EMC_PUTERM_EXTRA */
-			0x00000000, /* EMC_CDB_CNTL_2 */
-			0x00000004, /* EMC_QRST */
-			0x0000000f, /* EMC_RDV_MASK */
-			0x00000945, /* EMC_REFRESH */
-			0x00000000, /* EMC_BURST_REFRESH_NUM */
-			0x00000251, /* EMC_PRE_REFRESH_REQ_CNT */
-			0x00000001, /* EMC_PDEX2WR */
-			0x00000008, /* EMC_PDEX2RD */
-			0x00000001, /* EMC_PCHG2PDEN */
-			0x00000000, /* EMC_ACT2PDEN */
-			0x0000004d, /* EMC_AR2PDEN */
-			0x0000000e, /* EMC_RW2PDEN */
-			0x00000055, /* EMC_TXSR */
-			0x00000200, /* EMC_TXSRDLL */
-			0x00000004, /* EMC_TCKE */
-			0x00000004, /* EMC_TCKESR */
-			0x00000004, /* EMC_TPD */
-			0x0000000d, /* EMC_TFAW */
-			0x00000000, /* EMC_TRPAB */
-			0x00000004, /* EMC_TCLKSTABLE */
-			0x00000005, /* EMC_TCLKSTOP */
-			0x00000986, /* EMC_TREFBW */
-			0x00000006, /* EMC_QUSE_EXTRA */
-			0x00000020, /* EMC_ODT_WRITE */
-			0x00000000, /* EMC_ODT_READ */
-			0x0000ba88, /* EMC_FBIO_CFG5 */
-			0x002c00a0, /* EMC_CFG_DIG_DLL */
-			0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
-			0x00038000, /* EMC_DLL_XFORM_DQS4 */
-			0x00038000, /* EMC_DLL_XFORM_DQS5 */
-			0x00038000, /* EMC_DLL_XFORM_DQS6 */
-			0x00038000, /* EMC_DLL_XFORM_DQS7 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE4 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE5 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE6 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE7 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
-			0x001112a0, /* EMC_XM2CMDPADCTRL */
-			0x00000000, /* EMC_XM2CMDPADCTRL4 */
-			0x0001013d, /* EMC_XM2DQSPADCTRL2 */
-			0x00000000, /* EMC_XM2DQPADCTRL2 */
-			0x77ffc085, /* EMC_XM2CLKPADCTRL */
-			0x81f1f108, /* EMC_XM2COMPPADCTRL */
-			0x03035504, /* EMC_XM2VTTGENPADCTRL */
-			0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
-			0x0000003f, /* EMC_DSR_VTTGEN_DRV */
-			0x00000000, /* EMC_TXDSRVTTGEN */
-			0x02000000, /* EMC_FBIO_SPARE */
-			0x00000802, /* EMC_CTT_TERM_CTRL */
-			0x00020000, /* EMC_ZCAL_INTERVAL */
-			0x00000100, /* EMC_ZCAL_WAIT_CNT */
-			0x0171000f, /* EMC_MRS_WAIT_CNT */
-			0x0171000f, /* EMC_MRS_WAIT_CNT2 */
-			0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-			0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-			0x00000000, /* EMC_CTT */
-			0x00000000, /* EMC_CTT_DURATION */
-			0x80001395, /* EMC_DYN_SELF_REF_CONTROL */
-			0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
-			0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
-			0x0b000004, /* MC_EMEM_ARB_CFG */
-			0x8000016a, /* MC_EMEM_ARB_OUTSTANDING_REQ */
-			0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
-			0x00000002, /* MC_EMEM_ARB_TIMING_RP */
-			0x00000007, /* MC_EMEM_ARB_TIMING_RC */
-			0x00000004, /* MC_EMEM_ARB_TIMING_RAS */
-			0x00000006, /* MC_EMEM_ARB_TIMING_FAW */
-			0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
-			0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
-			0x00000007, /* MC_EMEM_ARB_TIMING_WAP2PRE */
-			0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
-			0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
-			0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
-			0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
-			0x06040202, /* MC_EMEM_ARB_DA_TURNS */
-			0x000b0607, /* MC_EMEM_ARB_DA_COVERS */
-			0x76e50f08, /* MC_EMEM_ARB_MISC0 */
-			0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
-		},
-		{
-			0x00000000, /* EMC_CDB_CNTL_1 */
-			0x00000006, /* EMC_FBIO_CFG6 */
-			0x00000007, /* EMC_QUSE */
-			0x00000005, /* EMC_EINPUT */
-			0x00000004, /* EMC_EINPUT_DURATION */
-			0x00038000, /* EMC_DLL_XFORM_DQS0 */
-			0x0000000b, /* EMC_QSAFE */
-			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
-			0x0000000e, /* EMC_RDV */
-			0x00249249, /* EMC_XM2DQSPADCTRL4 */
-			0x20820800, /* EMC_XM2DQSPADCTRL3 */
-			0x00048000, /* EMC_DLL_XFORM_DQ0 */
-			0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
-			0x00000000, /* EMC_DLL_XFORM_ADDR0 */
-			0x00000808, /* EMC_XM2CLKPADCTRL2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR1 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR2 */
-			0x00038000, /* EMC_DLL_XFORM_DQS1 */
-			0x00038000, /* EMC_DLL_XFORM_DQS2 */
-			0x00038000, /* EMC_DLL_XFORM_DQS3 */
-			0x00048000, /* EMC_DLL_XFORM_DQ1 */
-			0x00048000, /* EMC_DLL_XFORM_DQ2 */
-			0x00048000, /* EMC_DLL_XFORM_DQ3 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
-		},
-		{
-			0x00000000, /* EMC_CDB_CNTL_1 */
-			0x00000006, /* EMC_FBIO_CFG6 */
-			0x00000007, /* EMC_QUSE */
-			0x00000005, /* EMC_EINPUT */
-			0x00000004, /* EMC_EINPUT_DURATION */
-			0x00038000, /* EMC_DLL_XFORM_DQS0 */
-			0x0000000b, /* EMC_QSAFE */
-			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
-			0x0000000e, /* EMC_RDV */
-			0x00249249, /* EMC_XM2DQSPADCTRL4 */
-			0x20820800, /* EMC_XM2DQSPADCTRL3 */
-			0x00048000, /* EMC_DLL_XFORM_DQ0 */
-			0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
-			0x00000000, /* EMC_DLL_XFORM_ADDR0 */
-			0x00000808, /* EMC_XM2CLKPADCTRL2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR1 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR2 */
-			0x00038000, /* EMC_DLL_XFORM_DQS1 */
-			0x00038000, /* EMC_DLL_XFORM_DQS2 */
-			0x00038000, /* EMC_DLL_XFORM_DQS3 */
-			0x00048000, /* EMC_DLL_XFORM_DQ1 */
-			0x00048000, /* EMC_DLL_XFORM_DQ2 */
-			0x00048000, /* EMC_DLL_XFORM_DQ3 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
-		},
-		{
-			0x00000140, /* MC_PTSA_GRANT_DECREMENT */
-			0x00170017, /* MC_LATENCY_ALLOWANCE_G2_0 */
-			0x00170019, /* MC_LATENCY_ALLOWANCE_G2_1 */
-			0x001c001e, /* MC_LATENCY_ALLOWANCE_NV_0 */
-			0x0000001e, /* MC_LATENCY_ALLOWANCE_NV2_0 */
-			0x001e001e, /* MC_LATENCY_ALLOWANCE_NV_2 */
-			0x0029001e, /* MC_LATENCY_ALLOWANCE_NV_1 */
-			0x00000029, /* MC_LATENCY_ALLOWANCE_NV2_1 */
-			0x00290029, /* MC_LATENCY_ALLOWANCE_NV3 */
-			0x00ff0082, /* MC_LATENCY_ALLOWANCE_EPP_0 */
-			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
-		},
-		0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
-		0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
-		0x5320000e, /* EMC_CFG */
-		0x80000321, /* Mode Register 0 */
-		0x80100002, /* Mode Register 1 */
-		0x80200000, /* Mode Register 2 */
-		0x00000000, /* Mode Register 4 */
-		2680,       /* expected dvfs latency (ns) */
-	},
-	{
-		0x41,       /* Rev 4.0.3 */
-		408000,     /* SDRAM frequency */
-		1000,       /* min voltage */
-		"pll_p",    /* clock source id */
-		0x40000000, /* CLK_SOURCE_EMC */
-		99,         /* number of burst_regs */
-		30,         /* number of trim_regs (each channel) */
-		11,         /* number of up_down_regs */
-		{
-			0x00000012, /* EMC_RC */
-			0x00000069, /* EMC_RFC */
-			0x00000000, /* EMC_RFC_SLR */
-			0x0000000c, /* EMC_RAS */
-			0x00000004, /* EMC_RP */
-			0x00000005, /* EMC_R2W */
-			0x00000009, /* EMC_W2R */
-			0x00000002, /* EMC_R2P */
-			0x0000000c, /* EMC_W2P */
-			0x00000004, /* EMC_RD_RCD */
-			0x00000004, /* EMC_WR_RCD */
-			0x00000002, /* EMC_RRD */
-			0x00000001, /* EMC_REXT */
-			0x00000000, /* EMC_WEXT */
-			0x00000004, /* EMC_WDV */
-			0x0000000f, /* EMC_WDV_MASK */
-			0x00000007, /* EMC_IBDLY */
-			0x00010000, /* EMC_PUTERM_EXTRA */
-			0x00000000, /* EMC_CDB_CNTL_2 */
-			0x00000004, /* EMC_QRST */
-			0x00000010, /* EMC_RDV_MASK */
-			0x00000c2f, /* EMC_REFRESH */
-			0x00000000, /* EMC_BURST_REFRESH_NUM */
-			0x0000030b, /* EMC_PRE_REFRESH_REQ_CNT */
-			0x00000001, /* EMC_PDEX2WR */
-			0x00000008, /* EMC_PDEX2RD */
-			0x00000001, /* EMC_PCHG2PDEN */
-			0x00000000, /* EMC_ACT2PDEN */
-			0x00000066, /* EMC_AR2PDEN */
-			0x00000011, /* EMC_RW2PDEN */
-			0x0000006f, /* EMC_TXSR */
-			0x00000200, /* EMC_TXSRDLL */
-			0x00000004, /* EMC_TCKE */
-			0x00000004, /* EMC_TCKESR */
-			0x00000004, /* EMC_TPD */
-			0x00000011, /* EMC_TFAW */
-			0x00000000, /* EMC_TRPAB */
-			0x00000004, /* EMC_TCLKSTABLE */
-			0x00000005, /* EMC_TCLKSTOP */
-			0x00000c70, /* EMC_TREFBW */
-			0x00000006, /* EMC_QUSE_EXTRA */
-			0x00000020, /* EMC_ODT_WRITE */
-			0x00000000, /* EMC_ODT_READ */
-			0x0000ba88, /* EMC_FBIO_CFG5 */
-			0x002c0080, /* EMC_CFG_DIG_DLL */
-			0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
-			0x00028000, /* EMC_DLL_XFORM_DQS4 */
-			0x00028000, /* EMC_DLL_XFORM_DQS5 */
-			0x00028000, /* EMC_DLL_XFORM_DQS6 */
-			0x00028000, /* EMC_DLL_XFORM_DQS7 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE4 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE5 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE6 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE7 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
-			0x001112a0, /* EMC_XM2CMDPADCTRL */
-			0x00000000, /* EMC_XM2CMDPADCTRL4 */
-			0x0001013d, /* EMC_XM2DQSPADCTRL2 */
-			0x00000000, /* EMC_XM2DQPADCTRL2 */
-			0x77ffc085, /* EMC_XM2CLKPADCTRL */
-			0x81f1f108, /* EMC_XM2COMPPADCTRL */
-			0x03035504, /* EMC_XM2VTTGENPADCTRL */
-			0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
-			0x0000003f, /* EMC_DSR_VTTGEN_DRV */
-			0x00000000, /* EMC_TXDSRVTTGEN */
-			0x02000000, /* EMC_FBIO_SPARE */
-			0x00000802, /* EMC_CTT_TERM_CTRL */
-			0x00020000, /* EMC_ZCAL_INTERVAL */
-			0x00000100, /* EMC_ZCAL_WAIT_CNT */
-			0x0158000f, /* EMC_MRS_WAIT_CNT */
-			0x0158000f, /* EMC_MRS_WAIT_CNT2 */
-			0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-			0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-			0x00000000, /* EMC_CTT */
-			0x00000000, /* EMC_CTT_DURATION */
-			0x80001944, /* EMC_DYN_SELF_REF_CONTROL */
-			0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
-			0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
-			0x02000006, /* MC_EMEM_ARB_CFG */
-			0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */
-			0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
-			0x00000002, /* MC_EMEM_ARB_TIMING_RP */
-			0x00000009, /* MC_EMEM_ARB_TIMING_RC */
-			0x00000005, /* MC_EMEM_ARB_TIMING_RAS */
-			0x00000008, /* MC_EMEM_ARB_TIMING_FAW */
-			0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
-			0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
-			0x00000009, /* MC_EMEM_ARB_TIMING_WAP2PRE */
-			0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
-			0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
-			0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
-			0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
-			0x06040202, /* MC_EMEM_ARB_DA_TURNS */
-			0x000e0709, /* MC_EMEM_ARB_DA_COVERS */
-			0x7547130a, /* MC_EMEM_ARB_MISC0 */
-			0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
-		},
-		{
-			0x00000000, /* EMC_CDB_CNTL_1 */
-			0x00000006, /* EMC_FBIO_CFG6 */
-			0x00000007, /* EMC_QUSE */
-			0x00000005, /* EMC_EINPUT */
-			0x00000004, /* EMC_EINPUT_DURATION */
-			0x00028000, /* EMC_DLL_XFORM_DQS0 */
-			0x0000000c, /* EMC_QSAFE */
-			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
-			0x0000000e, /* EMC_RDV */
-			0x00249249, /* EMC_XM2DQSPADCTRL4 */
-			0x20820800, /* EMC_XM2DQSPADCTRL3 */
-			0x00038000, /* EMC_DLL_XFORM_DQ0 */
-			0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
-			0x00000000, /* EMC_DLL_XFORM_ADDR0 */
-			0x00000808, /* EMC_XM2CLKPADCTRL2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR1 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR2 */
-			0x00028000, /* EMC_DLL_XFORM_DQS1 */
-			0x00028000, /* EMC_DLL_XFORM_DQS2 */
-			0x00028000, /* EMC_DLL_XFORM_DQS3 */
-			0x00038000, /* EMC_DLL_XFORM_DQ1 */
-			0x00038000, /* EMC_DLL_XFORM_DQ2 */
-			0x00038000, /* EMC_DLL_XFORM_DQ3 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
-		},
-		{
-			0x00000000, /* EMC_CDB_CNTL_1 */
-			0x00000006, /* EMC_FBIO_CFG6 */
-			0x00000007, /* EMC_QUSE */
-			0x00000005, /* EMC_EINPUT */
-			0x00000004, /* EMC_EINPUT_DURATION */
-			0x00028000, /* EMC_DLL_XFORM_DQS0 */
-			0x0000000c, /* EMC_QSAFE */
-			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
-			0x0000000e, /* EMC_RDV */
-			0x00249249, /* EMC_XM2DQSPADCTRL4 */
-			0x20820800, /* EMC_XM2DQSPADCTRL3 */
-			0x00038000, /* EMC_DLL_XFORM_DQ0 */
-			0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
-			0x00000000, /* EMC_DLL_XFORM_ADDR0 */
-			0x00000808, /* EMC_XM2CLKPADCTRL2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR1 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR2 */
-			0x00028000, /* EMC_DLL_XFORM_DQS1 */
-			0x00028000, /* EMC_DLL_XFORM_DQS2 */
-			0x00028000, /* EMC_DLL_XFORM_DQS3 */
-			0x00038000, /* EMC_DLL_XFORM_DQ1 */
-			0x00038000, /* EMC_DLL_XFORM_DQ2 */
-			0x00038000, /* EMC_DLL_XFORM_DQ3 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
-		},
-		{
-			0x000000d1, /* MC_PTSA_GRANT_DECREMENT */
-			0x00110011, /* MC_LATENCY_ALLOWANCE_G2_0 */
-			0x00110013, /* MC_LATENCY_ALLOWANCE_G2_1 */
-			0x00150017, /* MC_LATENCY_ALLOWANCE_NV_0 */
-			0x00000017, /* MC_LATENCY_ALLOWANCE_NV2_0 */
-			0x00170017, /* MC_LATENCY_ALLOWANCE_NV_2 */
-			0x001f0017, /* MC_LATENCY_ALLOWANCE_NV_1 */
-			0x0000001f, /* MC_LATENCY_ALLOWANCE_NV2_1 */
-			0x001f001f, /* MC_LATENCY_ALLOWANCE_NV3 */
-			0x00d30064, /* MC_LATENCY_ALLOWANCE_EPP_0 */
-			0x00d300d3, /* MC_LATENCY_ALLOWANCE_EPP_1 */
-		},
-		0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
-		0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
-		0x53200006, /* EMC_CFG */
-		0x80000731, /* Mode Register 0 */
-		0x80100002, /* Mode Register 1 */
-		0x80200008, /* Mode Register 2 */
-		0x00000000, /* Mode Register 4 */
-		1750,       /* expected dvfs latency (ns) */
-	},
-	{
-		0x41,       /* Rev 4.0.3 */
-		450000,     /* SDRAM frequency */
-		1100,       /* min voltage */
-		"pll_m",    /* clock source id */
-		0x00000002, /* CLK_SOURCE_EMC */
-		99,         /* number of burst_regs */
-		30,         /* number of trim_regs (each channel) */
-		11,         /* number of up_down_regs */
-		{
-			0x00000014, /* EMC_RC */
-			0x00000074, /* EMC_RFC */
-			0x00000000, /* EMC_RFC_SLR */
-			0x0000000e, /* EMC_RAS */
-			0x00000005, /* EMC_RP */
-			0x00000005, /* EMC_R2W */
-			0x00000009, /* EMC_W2R */
-			0x00000002, /* EMC_R2P */
-			0x0000000c, /* EMC_W2P */
-			0x00000005, /* EMC_RD_RCD */
-			0x00000005, /* EMC_WR_RCD */
-			0x00000002, /* EMC_RRD */
-			0x00000001, /* EMC_REXT */
-			0x00000000, /* EMC_WEXT */
-			0x00000004, /* EMC_WDV */
-			0x0000000f, /* EMC_WDV_MASK */
-			0x00000007, /* EMC_IBDLY */
-			0x00010000, /* EMC_PUTERM_EXTRA */
-			0x00000000, /* EMC_CDB_CNTL_2 */
-			0x00000004, /* EMC_QRST */
-			0x00000010, /* EMC_RDV_MASK */
-			0x00000d79, /* EMC_REFRESH */
-			0x00000000, /* EMC_BURST_REFRESH_NUM */
-			0x0000035e, /* EMC_PRE_REFRESH_REQ_CNT */
-			0x00000001, /* EMC_PDEX2WR */
-			0x00000009, /* EMC_PDEX2RD */
-			0x00000001, /* EMC_PCHG2PDEN */
-			0x00000000, /* EMC_ACT2PDEN */
-			0x00000071, /* EMC_AR2PDEN */
-			0x00000011, /* EMC_RW2PDEN */
-			0x0000007a, /* EMC_TXSR */
-			0x00000200, /* EMC_TXSRDLL */
-			0x00000004, /* EMC_TCKE */
-			0x00000004, /* EMC_TCKESR */
-			0x00000004, /* EMC_TPD */
-			0x00000013, /* EMC_TFAW */
-			0x00000000, /* EMC_TRPAB */
-			0x00000004, /* EMC_TCLKSTABLE */
-			0x00000005, /* EMC_TCLKSTOP */
-			0x00000dba, /* EMC_TREFBW */
-			0x00000006, /* EMC_QUSE_EXTRA */
-			0x00000020, /* EMC_ODT_WRITE */
-			0x00000000, /* EMC_ODT_READ */
-			0x0000ba88, /* EMC_FBIO_CFG5 */
-			0x002c0080, /* EMC_CFG_DIG_DLL */
-			0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
-			0x00020000, /* EMC_DLL_XFORM_DQS4 */
-			0x00020000, /* EMC_DLL_XFORM_DQS5 */
-			0x00020000, /* EMC_DLL_XFORM_DQS6 */
-			0x00020000, /* EMC_DLL_XFORM_DQS7 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE4 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE5 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE6 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE7 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
-			0x001112a0, /* EMC_XM2CMDPADCTRL */
-			0x00000000, /* EMC_XM2CMDPADCTRL4 */
-			0x0000013d, /* EMC_XM2DQSPADCTRL2 */
-			0x00000000, /* EMC_XM2DQPADCTRL2 */
-			0x77ffc085, /* EMC_XM2CLKPADCTRL */
-			0x81f1f108, /* EMC_XM2COMPPADCTRL */
-			0x03035504, /* EMC_XM2VTTGENPADCTRL */
-			0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
-			0x0000003f, /* EMC_DSR_VTTGEN_DRV */
-			0x00000000, /* EMC_TXDSRVTTGEN */
-			0x02000000, /* EMC_FBIO_SPARE */
-			0x00000802, /* EMC_CTT_TERM_CTRL */
-			0x00020000, /* EMC_ZCAL_INTERVAL */
-			0x00000100, /* EMC_ZCAL_WAIT_CNT */
-			0x014d000f, /* EMC_MRS_WAIT_CNT */
-			0x014d000f, /* EMC_MRS_WAIT_CNT2 */
-			0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-			0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-			0x00000000, /* EMC_CTT */
-			0x00000000, /* EMC_CTT_DURATION */
-			0x80001bc7, /* EMC_DYN_SELF_REF_CONTROL */
-			0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
-			0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
-			0x0c000006, /* MC_EMEM_ARB_CFG */
-			0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */
-			0x00000002, /* MC_EMEM_ARB_TIMING_RCD */
-			0x00000003, /* MC_EMEM_ARB_TIMING_RP */
-			0x0000000b, /* MC_EMEM_ARB_TIMING_RC */
-			0x00000006, /* MC_EMEM_ARB_TIMING_RAS */
-			0x00000009, /* MC_EMEM_ARB_TIMING_FAW */
-			0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
-			0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
-			0x00000009, /* MC_EMEM_ARB_TIMING_WAP2PRE */
-			0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
-			0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
-			0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
-			0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
-			0x06040202, /* MC_EMEM_ARB_DA_TURNS */
-			0x000f080b, /* MC_EMEM_ARB_DA_COVERS */
-			0x74c7150c, /* MC_EMEM_ARB_MISC0 */
-			0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
-		},
-		{
-			0x00000000, /* EMC_CDB_CNTL_1 */
-			0x00000006, /* EMC_FBIO_CFG6 */
-			0x00000007, /* EMC_QUSE */
-			0x00000005, /* EMC_EINPUT */
-			0x00000004, /* EMC_EINPUT_DURATION */
-			0x00020000, /* EMC_DLL_XFORM_DQS0 */
-			0x0000000c, /* EMC_QSAFE */
-			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
-			0x0000000e, /* EMC_RDV */
-			0x00249249, /* EMC_XM2DQSPADCTRL4 */
-			0x20820800, /* EMC_XM2DQSPADCTRL3 */
-			0x00028000, /* EMC_DLL_XFORM_DQ0 */
-			0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
-			0x00000000, /* EMC_DLL_XFORM_ADDR0 */
-			0x00000808, /* EMC_XM2CLKPADCTRL2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR1 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR2 */
-			0x00020000, /* EMC_DLL_XFORM_DQS1 */
-			0x00020000, /* EMC_DLL_XFORM_DQS2 */
-			0x00020000, /* EMC_DLL_XFORM_DQS3 */
-			0x00028000, /* EMC_DLL_XFORM_DQ1 */
-			0x00028000, /* EMC_DLL_XFORM_DQ2 */
-			0x00028000, /* EMC_DLL_XFORM_DQ3 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
-		},
-		{
-			0x00000000, /* EMC_CDB_CNTL_1 */
-			0x00000006, /* EMC_FBIO_CFG6 */
-			0x00000007, /* EMC_QUSE */
-			0x00000005, /* EMC_EINPUT */
-			0x00000004, /* EMC_EINPUT_DURATION */
-			0x00020000, /* EMC_DLL_XFORM_DQS0 */
-			0x0000000c, /* EMC_QSAFE */
-			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
-			0x0000000e, /* EMC_RDV */
-			0x00249249, /* EMC_XM2DQSPADCTRL4 */
-			0x20820800, /* EMC_XM2DQSPADCTRL3 */
-			0x00028000, /* EMC_DLL_XFORM_DQ0 */
-			0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
-			0x00000000, /* EMC_DLL_XFORM_ADDR0 */
-			0x00000808, /* EMC_XM2CLKPADCTRL2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR1 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR2 */
-			0x00020000, /* EMC_DLL_XFORM_DQS1 */
-			0x00020000, /* EMC_DLL_XFORM_DQS2 */
-			0x00020000, /* EMC_DLL_XFORM_DQS3 */
-			0x00028000, /* EMC_DLL_XFORM_DQ1 */
-			0x00028000, /* EMC_DLL_XFORM_DQ2 */
-			0x00028000, /* EMC_DLL_XFORM_DQ3 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
-		},
-		{
-			0x000000e6, /* MC_PTSA_GRANT_DECREMENT */
-			0x00100010, /* MC_LATENCY_ALLOWANCE_G2_0 */
-			0x00100011, /* MC_LATENCY_ALLOWANCE_G2_1 */
-			0x00130015, /* MC_LATENCY_ALLOWANCE_NV_0 */
-			0x00000015, /* MC_LATENCY_ALLOWANCE_NV2_0 */
-			0x00150015, /* MC_LATENCY_ALLOWANCE_NV_2 */
-			0x001c0015, /* MC_LATENCY_ALLOWANCE_NV_1 */
-			0x0000001c, /* MC_LATENCY_ALLOWANCE_NV2_1 */
-			0x001c001c, /* MC_LATENCY_ALLOWANCE_NV3 */
-			0x00c0005a, /* MC_LATENCY_ALLOWANCE_EPP_0 */
-			0x00c000c0, /* MC_LATENCY_ALLOWANCE_EPP_1 */
-		},
-		0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
-		0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
-		0x53200006, /* EMC_CFG */
-		0x80000731, /* Mode Register 0 */
-		0x80100002, /* Mode Register 1 */
-		0x80200008, /* Mode Register 2 */
-		0x00000000, /* Mode Register 4 */
-		1750,       /* expected dvfs latency (ns) */
-	},
-	{
-		0x41,       /* Rev 4.0.3 */
-		528000,     /* SDRAM frequency */
-		1100,       /* min voltage */
-		"pll_m",    /* clock source id */
-		0x80000000, /* CLK_SOURCE_EMC */
-		99,         /* number of burst_regs */
-		30,         /* number of trim_regs (each channel) */
-		11,         /* number of up_down_regs */
-		{
-			0x00000018, /* EMC_RC */
-			0x00000088, /* EMC_RFC */
-			0x00000000, /* EMC_RFC_SLR */
-			0x00000010, /* EMC_RAS */
-			0x00000006, /* EMC_RP */
-			0x00000006, /* EMC_R2W */
-			0x00000009, /* EMC_W2R */
-			0x00000002, /* EMC_R2P */
-			0x0000000d, /* EMC_W2P */
-			0x00000006, /* EMC_RD_RCD */
-			0x00000006, /* EMC_WR_RCD */
-			0x00000002, /* EMC_RRD */
-			0x00000001, /* EMC_REXT */
-			0x00000000, /* EMC_WEXT */
-			0x00000005, /* EMC_WDV */
-			0x0000000f, /* EMC_WDV_MASK */
-			0x00000009, /* EMC_IBDLY */
-			0x00010000, /* EMC_PUTERM_EXTRA */
-			0x00000000, /* EMC_CDB_CNTL_2 */
-			0x00000006, /* EMC_QRST */
-			0x00000012, /* EMC_RDV_MASK */
-			0x00000fde, /* EMC_REFRESH */
-			0x00000000, /* EMC_BURST_REFRESH_NUM */
-			0x000003f7, /* EMC_PRE_REFRESH_REQ_CNT */
-			0x00000002, /* EMC_PDEX2WR */
-			0x0000000b, /* EMC_PDEX2RD */
-			0x00000001, /* EMC_PCHG2PDEN */
-			0x00000000, /* EMC_ACT2PDEN */
-			0x00000085, /* EMC_AR2PDEN */
-			0x00000012, /* EMC_RW2PDEN */
-			0x0000008f, /* EMC_TXSR */
-			0x00000200, /* EMC_TXSRDLL */
-			0x00000004, /* EMC_TCKE */
-			0x00000004, /* EMC_TCKESR */
-			0x00000004, /* EMC_TPD */
-			0x00000016, /* EMC_TFAW */
-			0x00000000, /* EMC_TRPAB */
-			0x00000005, /* EMC_TCLKSTABLE */
-			0x00000006, /* EMC_TCLKSTOP */
-			0x0000101f, /* EMC_TREFBW */
-			0x00000008, /* EMC_QUSE_EXTRA */
-			0x00000020, /* EMC_ODT_WRITE */
-			0x00000000, /* EMC_ODT_READ */
-			0x0000ba88, /* EMC_FBIO_CFG5 */
-			0xf0120091, /* EMC_CFG_DIG_DLL */
-			0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
-			0x00000009, /* EMC_DLL_XFORM_DQS4 */
-			0x00000009, /* EMC_DLL_XFORM_DQS5 */
-			0x00000009, /* EMC_DLL_XFORM_DQS6 */
-			0x00000009, /* EMC_DLL_XFORM_DQS7 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE4 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE5 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE6 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE7 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
-			0x001112a0, /* EMC_XM2CMDPADCTRL */
-			0x00000000, /* EMC_XM2CMDPADCTRL4 */
-			0x0000013d, /* EMC_XM2DQSPADCTRL2 */
-			0x00000000, /* EMC_XM2DQPADCTRL2 */
-			0x77ffc085, /* EMC_XM2CLKPADCTRL */
-			0x81f1f108, /* EMC_XM2COMPPADCTRL */
-			0x03035504, /* EMC_XM2VTTGENPADCTRL */
-			0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
-			0x0000003f, /* EMC_DSR_VTTGEN_DRV */
-			0x00000000, /* EMC_TXDSRVTTGEN */
-			0x02000000, /* EMC_FBIO_SPARE */
-			0x00000802, /* EMC_CTT_TERM_CTRL */
-			0x00020000, /* EMC_ZCAL_INTERVAL */
-			0x00000100, /* EMC_ZCAL_WAIT_CNT */
-			0x0139000f, /* EMC_MRS_WAIT_CNT */
-			0x0139000f, /* EMC_MRS_WAIT_CNT2 */
-			0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-			0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-			0x00000000, /* EMC_CTT */
-			0x00000000, /* EMC_CTT_DURATION */
-			0x80002073, /* EMC_DYN_SELF_REF_CONTROL */
-			0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
-			0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
-			0x0f000007, /* MC_EMEM_ARB_CFG */
-			0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */
-			0x00000002, /* MC_EMEM_ARB_TIMING_RCD */
-			0x00000003, /* MC_EMEM_ARB_TIMING_RP */
-			0x0000000c, /* MC_EMEM_ARB_TIMING_RC */
-			0x00000007, /* MC_EMEM_ARB_TIMING_RAS */
-			0x0000000a, /* MC_EMEM_ARB_TIMING_FAW */
-			0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
-			0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
-			0x00000009, /* MC_EMEM_ARB_TIMING_WAP2PRE */
-			0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
-			0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
-			0x00000005, /* MC_EMEM_ARB_TIMING_R2W */
-			0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
-			0x06050202, /* MC_EMEM_ARB_DA_TURNS */
-			0x0010090c, /* MC_EMEM_ARB_DA_COVERS */
-			0x7428180d, /* MC_EMEM_ARB_MISC0 */
-			0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
-		},
-		{
-			0x00000000, /* EMC_CDB_CNTL_1 */
-			0x00000006, /* EMC_FBIO_CFG6 */
-			0x00000009, /* EMC_QUSE */
-			0x00000007, /* EMC_EINPUT */
-			0x00000004, /* EMC_EINPUT_DURATION */
-			0x00000009, /* EMC_DLL_XFORM_DQS0 */
-			0x0000000c, /* EMC_QSAFE */
-			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
-			0x00000010, /* EMC_RDV */
-			0x00249249, /* EMC_XM2DQSPADCTRL4 */
-			0x20820800, /* EMC_XM2DQSPADCTRL3 */
-			0x0000000b, /* EMC_DLL_XFORM_DQ0 */
-			0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
-			0x00000000, /* EMC_DLL_XFORM_ADDR0 */
-			0x00000808, /* EMC_XM2CLKPADCTRL2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR1 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR2 */
-			0x00000009, /* EMC_DLL_XFORM_DQS1 */
-			0x00000009, /* EMC_DLL_XFORM_DQS2 */
-			0x00000009, /* EMC_DLL_XFORM_DQS3 */
-			0x0000000b, /* EMC_DLL_XFORM_DQ1 */
-			0x0000000b, /* EMC_DLL_XFORM_DQ2 */
-			0x0000000b, /* EMC_DLL_XFORM_DQ3 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
-		},
-		{
-			0x00000000, /* EMC_CDB_CNTL_1 */
-			0x00000006, /* EMC_FBIO_CFG6 */
-			0x00000009, /* EMC_QUSE */
-			0x00000007, /* EMC_EINPUT */
-			0x00000004, /* EMC_EINPUT_DURATION */
-			0x00000009, /* EMC_DLL_XFORM_DQS0 */
-			0x0000000c, /* EMC_QSAFE */
-			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
-			0x00000010, /* EMC_RDV */
-			0x00249249, /* EMC_XM2DQSPADCTRL4 */
-			0x20820800, /* EMC_XM2DQSPADCTRL3 */
-			0x0000000b, /* EMC_DLL_XFORM_DQ0 */
-			0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
-			0x00000000, /* EMC_DLL_XFORM_ADDR0 */
-			0x00000808, /* EMC_XM2CLKPADCTRL2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR1 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR2 */
-			0x00000009, /* EMC_DLL_XFORM_DQS1 */
-			0x00000009, /* EMC_DLL_XFORM_DQS2 */
-			0x00000009, /* EMC_DLL_XFORM_DQS3 */
-			0x0000000b, /* EMC_DLL_XFORM_DQ1 */
-			0x0000000b, /* EMC_DLL_XFORM_DQ2 */
-			0x0000000b, /* EMC_DLL_XFORM_DQ3 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
-		},
-		{
-			0x0000010e, /* MC_PTSA_GRANT_DECREMENT */
-			0x000d000d, /* MC_LATENCY_ALLOWANCE_G2_0 */
-			0x000d000f, /* MC_LATENCY_ALLOWANCE_G2_1 */
-			0x00100012, /* MC_LATENCY_ALLOWANCE_NV_0 */
-			0x00000012, /* MC_LATENCY_ALLOWANCE_NV2_0 */
-			0x00120012, /* MC_LATENCY_ALLOWANCE_NV_2 */
-			0x00180012, /* MC_LATENCY_ALLOWANCE_NV_1 */
-			0x00000018, /* MC_LATENCY_ALLOWANCE_NV2_1 */
-			0x00180018, /* MC_LATENCY_ALLOWANCE_NV3 */
-			0x00a3004d, /* MC_LATENCY_ALLOWANCE_EPP_0 */
-			0x00a300a3, /* MC_LATENCY_ALLOWANCE_EPP_1 */
-		},
-		0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
-		0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
-		0x53200004, /* EMC_CFG */
-		0x80000941, /* Mode Register 0 */
-		0x80100002, /* Mode Register 1 */
-		0x80200008, /* Mode Register 2 */
-		0x00000000, /* Mode Register 4 */
-		1440,       /* expected dvfs latency (ns) */
-	},
-	{
-		0x41,       /* Rev 4.0.3 */
-		624000,     /* SDRAM frequency */
-		1100,       /* min voltage */
-		"pll_c",    /* clock source id */
-		0x24000000, /* CLK_SOURCE_EMC */
-		99,         /* number of burst_regs */
-		30,         /* number of trim_regs (each channel) */
-		11,         /* number of up_down_regs */
-		{
-			0x0000001c, /* EMC_RC */
-			0x000000a1, /* EMC_RFC */
-			0x00000000, /* EMC_RFC_SLR */
-			0x00000014, /* EMC_RAS */
-			0x00000007, /* EMC_RP */
-			0x00000007, /* EMC_R2W */
-			0x0000000b, /* EMC_W2R */
-			0x00000003, /* EMC_R2P */
-			0x00000010, /* EMC_W2P */
-			0x00000007, /* EMC_RD_RCD */
-			0x00000007, /* EMC_WR_RCD */
-			0x00000002, /* EMC_RRD */
-			0x00000001, /* EMC_REXT */
-			0x00000000, /* EMC_WEXT */
-			0x00000005, /* EMC_WDV */
-			0x0000000f, /* EMC_WDV_MASK */
-			0x0000000b, /* EMC_IBDLY */
-			0x00010000, /* EMC_PUTERM_EXTRA */
-			0x00000000, /* EMC_CDB_CNTL_2 */
-			0x00000007, /* EMC_QRST */
-			0x00000013, /* EMC_RDV_MASK */
-			0x000012cb, /* EMC_REFRESH */
-			0x00000000, /* EMC_BURST_REFRESH_NUM */
-			0x000004b2, /* EMC_PRE_REFRESH_REQ_CNT */
-			0x00000002, /* EMC_PDEX2WR */
-			0x0000000d, /* EMC_PDEX2RD */
-			0x00000001, /* EMC_PCHG2PDEN */
-			0x00000000, /* EMC_ACT2PDEN */
-			0x000000a5, /* EMC_AR2PDEN */
-			0x00000015, /* EMC_RW2PDEN */
-			0x000000a9, /* EMC_TXSR */
-			0x00000200, /* EMC_TXSRDLL */
-			0x00000005, /* EMC_TCKE */
-			0x00000005, /* EMC_TCKESR */
-			0x00000005, /* EMC_TPD */
-			0x00000019, /* EMC_TFAW */
-			0x00000000, /* EMC_TRPAB */
-			0x00000006, /* EMC_TCLKSTABLE */
-			0x00000007, /* EMC_TCLKSTOP */
-			0x0000130b, /* EMC_TREFBW */
-			0x00000009, /* EMC_QUSE_EXTRA */
-			0x00000020, /* EMC_ODT_WRITE */
-			0x00000000, /* EMC_ODT_READ */
-			0x0000ba88, /* EMC_FBIO_CFG5 */
-			0xf00d0191, /* EMC_CFG_DIG_DLL */
-			0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
-			0x0000000a, /* EMC_DLL_XFORM_DQS4 */
-			0x0000000a, /* EMC_DLL_XFORM_DQS5 */
-			0x0000000a, /* EMC_DLL_XFORM_DQS6 */
-			0x0000000a, /* EMC_DLL_XFORM_DQS7 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE4 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE5 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE6 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE7 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
-			0x001112a0, /* EMC_XM2CMDPADCTRL */
-			0x00000000, /* EMC_XM2CMDPADCTRL4 */
-			0x0000013d, /* EMC_XM2DQSPADCTRL2 */
-			0x00000000, /* EMC_XM2DQPADCTRL2 */
-			0x77ffc085, /* EMC_XM2CLKPADCTRL */
-			0x81f1f108, /* EMC_XM2COMPPADCTRL */
-			0x07077504, /* EMC_XM2VTTGENPADCTRL */
-			0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
-			0x0000003f, /* EMC_DSR_VTTGEN_DRV */
-			0x00000000, /* EMC_TXDSRVTTGEN */
-			0x02000000, /* EMC_FBIO_SPARE */
-			0x00000802, /* EMC_CTT_TERM_CTRL */
-			0x00020000, /* EMC_ZCAL_INTERVAL */
-			0x00000100, /* EMC_ZCAL_WAIT_CNT */
-			0x0122000f, /* EMC_MRS_WAIT_CNT */
-			0x0122000f, /* EMC_MRS_WAIT_CNT2 */
-			0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-			0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-			0x00000000, /* EMC_CTT */
-			0x00000000, /* EMC_CTT_DURATION */
-			0x80002626, /* EMC_DYN_SELF_REF_CONTROL */
-			0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
-			0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
-			0x06000009, /* MC_EMEM_ARB_CFG */
-			0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */
-			0x00000003, /* MC_EMEM_ARB_TIMING_RCD */
-			0x00000004, /* MC_EMEM_ARB_TIMING_RP */
-			0x0000000f, /* MC_EMEM_ARB_TIMING_RC */
-			0x00000009, /* MC_EMEM_ARB_TIMING_RAS */
-			0x0000000c, /* MC_EMEM_ARB_TIMING_FAW */
-			0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
-			0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
-			0x0000000b, /* MC_EMEM_ARB_TIMING_WAP2PRE */
-			0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
-			0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
-			0x00000005, /* MC_EMEM_ARB_TIMING_R2W */
-			0x00000007, /* MC_EMEM_ARB_TIMING_W2R */
-			0x07050202, /* MC_EMEM_ARB_DA_TURNS */
-			0x00130b0f, /* MC_EMEM_ARB_DA_COVERS */
-			0x736a1d10, /* MC_EMEM_ARB_MISC0 */
-			0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
-		},
-		{
-			0x00000000, /* EMC_CDB_CNTL_1 */
-			0x00000006, /* EMC_FBIO_CFG6 */
-			0x0000000a, /* EMC_QUSE */
-			0x00000007, /* EMC_EINPUT */
-			0x00000005, /* EMC_EINPUT_DURATION */
-			0x0000000a, /* EMC_DLL_XFORM_DQS0 */
-			0x0000000c, /* EMC_QSAFE */
-			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
-			0x00000011, /* EMC_RDV */
-			0x00249249, /* EMC_XM2DQSPADCTRL4 */
-			0x20820800, /* EMC_XM2DQSPADCTRL3 */
-			0x0000000b, /* EMC_DLL_XFORM_DQ0 */
-			0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
-			0x00000000, /* EMC_DLL_XFORM_ADDR0 */
-			0x00000808, /* EMC_XM2CLKPADCTRL2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR1 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR2 */
-			0x0000000a, /* EMC_DLL_XFORM_DQS1 */
-			0x0000000a, /* EMC_DLL_XFORM_DQS2 */
-			0x0000000a, /* EMC_DLL_XFORM_DQS3 */
-			0x0000000a, /* EMC_DLL_XFORM_DQ1 */
-			0x0000000b, /* EMC_DLL_XFORM_DQ2 */
-			0x0000000b, /* EMC_DLL_XFORM_DQ3 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
-		},
-		{
-			0x00000000, /* EMC_CDB_CNTL_1 */
-			0x00000006, /* EMC_FBIO_CFG6 */
-			0x0000000a, /* EMC_QUSE */
-			0x00000007, /* EMC_EINPUT */
-			0x00000005, /* EMC_EINPUT_DURATION */
-			0x0000000a, /* EMC_DLL_XFORM_DQS0 */
-			0x0000000c, /* EMC_QSAFE */
-			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
-			0x00000011, /* EMC_RDV */
-			0x00249249, /* EMC_XM2DQSPADCTRL4 */
-			0x20820800, /* EMC_XM2DQSPADCTRL3 */
-			0x0000000a, /* EMC_DLL_XFORM_DQ0 */
-			0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
-			0x00000000, /* EMC_DLL_XFORM_ADDR0 */
-			0x00000808, /* EMC_XM2CLKPADCTRL2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR1 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR2 */
-			0x0000000a, /* EMC_DLL_XFORM_DQS1 */
-			0x0000000a, /* EMC_DLL_XFORM_DQS2 */
-			0x0000000a, /* EMC_DLL_XFORM_DQS3 */
-			0x0000000a, /* EMC_DLL_XFORM_DQ1 */
-			0x0000000a, /* EMC_DLL_XFORM_DQ2 */
-			0x0000000a, /* EMC_DLL_XFORM_DQ3 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
-		},
-		{
-			0x0000013f, /* MC_PTSA_GRANT_DECREMENT */
-			0x000b000b, /* MC_LATENCY_ALLOWANCE_G2_0 */
-			0x000b000c, /* MC_LATENCY_ALLOWANCE_G2_1 */
-			0x000e000f, /* MC_LATENCY_ALLOWANCE_NV_0 */
-			0x0000000f, /* MC_LATENCY_ALLOWANCE_NV2_0 */
-			0x000f000f, /* MC_LATENCY_ALLOWANCE_NV_2 */
-			0x0014000f, /* MC_LATENCY_ALLOWANCE_NV_1 */
-			0x00000014, /* MC_LATENCY_ALLOWANCE_NV2_1 */
-			0x00140014, /* MC_LATENCY_ALLOWANCE_NV3 */
-			0x008a0041, /* MC_LATENCY_ALLOWANCE_EPP_0 */
-			0x008a008a, /* MC_LATENCY_ALLOWANCE_EPP_1 */
-		},
-		0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
-		0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
-		0x53200000, /* EMC_CFG */
-		0x80000b61, /* Mode Register 0 */
-		0x80100002, /* Mode Register 1 */
-		0x80200010, /* Mode Register 2 */
-		0x00000000, /* Mode Register 4 */
-		1440,       /* expected dvfs latency (ns) */
-	},
-	{
-		0x41,       /* Rev 4.0.3 */
-		792000,     /* SDRAM frequency */
-		1100,       /* min voltage */
-		"pll_m",    /* clock source id */
-		0x80000000, /* CLK_SOURCE_EMC */
-		99,         /* number of burst_regs */
-		30,         /* number of trim_regs (each channel) */
-		11,         /* number of up_down_regs */
-		{
-			0x00000025, /* EMC_RC */
-			0x000000cd, /* EMC_RFC */
-			0x00000000, /* EMC_RFC_SLR */
-			0x00000019, /* EMC_RAS */
-			0x0000000a, /* EMC_RP */
-			0x00000009, /* EMC_R2W */
-			0x0000000d, /* EMC_W2R */
-			0x00000004, /* EMC_R2P */
-			0x00000013, /* EMC_W2P */
-			0x0000000a, /* EMC_RD_RCD */
-			0x0000000a, /* EMC_WR_RCD */
-			0x00000003, /* EMC_RRD */
-			0x00000001, /* EMC_REXT */
-			0x00000000, /* EMC_WEXT */
-			0x00000006, /* EMC_WDV */
-			0x0000000f, /* EMC_WDV_MASK */
-			0x0000000c, /* EMC_IBDLY */
-			0x000d000a, /* EMC_PUTERM_EXTRA */
-			0x00000000, /* EMC_CDB_CNTL_2 */
-			0x00000009, /* EMC_QRST */
-			0x00000016, /* EMC_RDV_MASK */
-			0x000017ee, /* EMC_REFRESH */
-			0x00000000, /* EMC_BURST_REFRESH_NUM */
-			0x000005fb, /* EMC_PRE_REFRESH_REQ_CNT */
-			0x00000003, /* EMC_PDEX2WR */
-			0x00000012, /* EMC_PDEX2RD */
-			0x00000001, /* EMC_PCHG2PDEN */
-			0x00000000, /* EMC_ACT2PDEN */
-			0x000000c6, /* EMC_AR2PDEN */
-			0x00000018, /* EMC_RW2PDEN */
-			0x000000d7, /* EMC_TXSR */
-			0x00000200, /* EMC_TXSRDLL */
-			0x00000005, /* EMC_TCKE */
-			0x00000005, /* EMC_TCKESR */
-			0x00000005, /* EMC_TPD */
-			0x00000020, /* EMC_TFAW */
-			0x00000000, /* EMC_TRPAB */
-			0x00000007, /* EMC_TCLKSTABLE */
-			0x00000008, /* EMC_TCLKSTOP */
-			0x0000182f, /* EMC_TREFBW */
-			0x0000000b, /* EMC_QUSE_EXTRA */
-			0x80000000, /* EMC_ODT_WRITE */
-			0x00000000, /* EMC_ODT_READ */
-			0x0000ba88, /* EMC_FBIO_CFG5 */
-			0xf0070191, /* EMC_CFG_DIG_DLL */
-			0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
-			0x00000008, /* EMC_DLL_XFORM_DQS4 */
-			0x00000008, /* EMC_DLL_XFORM_DQS5 */
-			0x00000008, /* EMC_DLL_XFORM_DQS6 */
-			0x00000008, /* EMC_DLL_XFORM_DQS7 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE4 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE5 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE6 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE7 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
-			0x001112a0, /* EMC_XM2CMDPADCTRL */
-			0x00000000, /* EMC_XM2CMDPADCTRL4 */
-			0x0000013d, /* EMC_XM2DQSPADCTRL2 */
-			0x00000000, /* EMC_XM2DQPADCTRL2 */
-			0x77ffc085, /* EMC_XM2CLKPADCTRL */
-			0x81f1f508, /* EMC_XM2COMPPADCTRL */
-			0x07076604, /* EMC_XM2VTTGENPADCTRL */
-			0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
-			0x0000003f, /* EMC_DSR_VTTGEN_DRV */
-			0x00000000, /* EMC_TXDSRVTTGEN */
-			0x02000000, /* EMC_FBIO_SPARE */
-			0x00000802, /* EMC_CTT_TERM_CTRL */
-			0x00020000, /* EMC_ZCAL_INTERVAL */
-			0x00000100, /* EMC_ZCAL_WAIT_CNT */
-			0x00f8000f, /* EMC_MRS_WAIT_CNT */
-			0x00f8000f, /* EMC_MRS_WAIT_CNT2 */
-			0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-			0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-			0x00000000, /* EMC_CTT */
-			0x00000000, /* EMC_CTT_DURATION */
-			0x8000302b, /* EMC_DYN_SELF_REF_CONTROL */
-			0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
-			0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
-			0x0e00000b, /* MC_EMEM_ARB_CFG */
-			0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */
-			0x00000004, /* MC_EMEM_ARB_TIMING_RCD */
-			0x00000005, /* MC_EMEM_ARB_TIMING_RP */
-			0x00000013, /* MC_EMEM_ARB_TIMING_RC */
-			0x0000000c, /* MC_EMEM_ARB_TIMING_RAS */
-			0x0000000f, /* MC_EMEM_ARB_TIMING_FAW */
-			0x00000002, /* MC_EMEM_ARB_TIMING_RRD */
-			0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
-			0x0000000c, /* MC_EMEM_ARB_TIMING_WAP2PRE */
-			0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
-			0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
-			0x00000006, /* MC_EMEM_ARB_TIMING_R2W */
-			0x00000008, /* MC_EMEM_ARB_TIMING_W2R */
-			0x08060202, /* MC_EMEM_ARB_DA_TURNS */
-			0x00170e13, /* MC_EMEM_ARB_DA_COVERS */
-			0x734c2414, /* MC_EMEM_ARB_MISC0 */
-			0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
-		},
-		{
-			0x00000000, /* EMC_CDB_CNTL_1 */
-			0x00000006, /* EMC_FBIO_CFG6 */
-			0x0000000d, /* EMC_QUSE */
-			0x0000000a, /* EMC_EINPUT */
-			0x00000005, /* EMC_EINPUT_DURATION */
-			0x00000008, /* EMC_DLL_XFORM_DQS0 */
-			0x0000000d, /* EMC_QSAFE */
-			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
-			0x00000015, /* EMC_RDV */
-			0x00249249, /* EMC_XM2DQSPADCTRL4 */
-			0x20820800, /* EMC_XM2DQSPADCTRL3 */
-			0x0000000a, /* EMC_DLL_XFORM_DQ0 */
-			0xa0f10f0f, /* EMC_AUTO_CAL_CONFIG */
-			0x00004000, /* EMC_DLL_XFORM_ADDR0 */
-			0x00000a0a, /* EMC_XM2CLKPADCTRL2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR1 */
-			0x00004000, /* EMC_DLL_XFORM_ADDR2 */
-			0x00000008, /* EMC_DLL_XFORM_DQS1 */
-			0x00000008, /* EMC_DLL_XFORM_DQS2 */
-			0x00000008, /* EMC_DLL_XFORM_DQS3 */
-			0x0000000a, /* EMC_DLL_XFORM_DQ1 */
-			0x0000000c, /* EMC_DLL_XFORM_DQ2 */
-			0x0000000a, /* EMC_DLL_XFORM_DQ3 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
-		},
-		{
-			0x00000000, /* EMC_CDB_CNTL_1 */
-			0x00000006, /* EMC_FBIO_CFG6 */
-			0x0000000d, /* EMC_QUSE */
-			0x0000000a, /* EMC_EINPUT */
-			0x00000005, /* EMC_EINPUT_DURATION */
-			0x00000008, /* EMC_DLL_XFORM_DQS0 */
-			0x0000000d, /* EMC_QSAFE */
-			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
-			0x00000015, /* EMC_RDV */
-			0x00249249, /* EMC_XM2DQSPADCTRL4 */
-			0x20820800, /* EMC_XM2DQSPADCTRL3 */
-			0x0000000a, /* EMC_DLL_XFORM_DQ0 */
-			0xa8f10f0f, /* EMC_AUTO_CAL_CONFIG */
-			0x00004000, /* EMC_DLL_XFORM_ADDR0 */
-			0x00000a0a, /* EMC_XM2CLKPADCTRL2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR1 */
-			0x00004000, /* EMC_DLL_XFORM_ADDR2 */
-			0x00000008, /* EMC_DLL_XFORM_DQS1 */
-			0x00000008, /* EMC_DLL_XFORM_DQS2 */
-			0x00000008, /* EMC_DLL_XFORM_DQS3 */
-			0x0000000a, /* EMC_DLL_XFORM_DQ1 */
-			0x0000000c, /* EMC_DLL_XFORM_DQ2 */
-			0x0000000a, /* EMC_DLL_XFORM_DQ3 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
-		},
-		{
-			0x00000196, /* MC_PTSA_GRANT_DECREMENT */
-			0x00090009, /* MC_LATENCY_ALLOWANCE_G2_0 */
-			0x0009000a, /* MC_LATENCY_ALLOWANCE_G2_1 */
-			0x000b000c, /* MC_LATENCY_ALLOWANCE_NV_0 */
-			0x0000000c, /* MC_LATENCY_ALLOWANCE_NV2_0 */
-			0x000c000c, /* MC_LATENCY_ALLOWANCE_NV_2 */
-			0x0010000c, /* MC_LATENCY_ALLOWANCE_NV_1 */
-			0x00000010, /* MC_LATENCY_ALLOWANCE_NV2_1 */
-			0x00100010, /* MC_LATENCY_ALLOWANCE_NV3 */
-			0x006d0033, /* MC_LATENCY_ALLOWANCE_EPP_0 */
-			0x006d006d, /* MC_LATENCY_ALLOWANCE_EPP_1 */
-		},
-		0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
-		0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
-		0x53300000, /* EMC_CFG */
-		0x80000d05, /* Mode Register 0 */
-		0x80100002, /* Mode Register 1 */
-		0x80200418, /* Mode Register 2 */
-		0x00000000, /* Mode Register 4 */
-		1200,       /* expected dvfs latency (ns) */
-	},
-	{
-		0x41,       /* Rev 4.0.3 */
-		900000,     /* SDRAM frequency */
-		1200,       /* min voltage */
-		"pll_m",    /* clock source id */
-		0x80000000, /* CLK_SOURCE_EMC */
-		99,         /* number of burst_regs */
-		30,         /* number of trim_regs (each channel) */
-		11,         /* number of up_down_regs */
-		{
-			0x0000002a, /* EMC_RC */
-			0x000000e9, /* EMC_RFC */
-			0x00000000, /* EMC_RFC_SLR */
-			0x0000001d, /* EMC_RAS */
-			0x0000000b, /* EMC_RP */
-			0x00000008, /* EMC_R2W */
-			0x0000000f, /* EMC_W2R */
-			0x00000005, /* EMC_R2P */
-			0x00000016, /* EMC_W2P */
-			0x0000000b, /* EMC_RD_RCD */
-			0x0000000b, /* EMC_WR_RCD */
-			0x00000004, /* EMC_RRD */
-			0x00000001, /* EMC_REXT */
-			0x00000000, /* EMC_WEXT */
-			0x00000007, /* EMC_WDV */
-			0x0000000f, /* EMC_WDV_MASK */
-			0x0000000d, /* EMC_IBDLY */
-			0x00010000, /* EMC_PUTERM_EXTRA */
-			0x00000000, /* EMC_CDB_CNTL_2 */
-			0x0000000a, /* EMC_QRST */
-			0x00000017, /* EMC_RDV_MASK */
-			0x00001b33, /* EMC_REFRESH */
-			0x00000000, /* EMC_BURST_REFRESH_NUM */
-			0x000006cc, /* EMC_PRE_REFRESH_REQ_CNT */
-			0x00000004, /* EMC_PDEX2WR */
-			0x00000014, /* EMC_PDEX2RD */
-			0x00000001, /* EMC_PCHG2PDEN */
-			0x00000000, /* EMC_ACT2PDEN */
-			0x000000e0, /* EMC_AR2PDEN */
-			0x0000001b, /* EMC_RW2PDEN */
-			0x000000f4, /* EMC_TXSR */
-			0x00000200, /* EMC_TXSRDLL */
-			0x00000006, /* EMC_TCKE */
-			0x00000006, /* EMC_TCKESR */
-			0x00000006, /* EMC_TPD */
-			0x00000025, /* EMC_TFAW */
-			0x00000000, /* EMC_TRPAB */
-			0x00000008, /* EMC_TCLKSTABLE */
-			0x00000009, /* EMC_TCLKSTOP */
-			0x00001b74, /* EMC_TREFBW */
-			0x00000000, /* EMC_QUSE_EXTRA */
-			0x80000000, /* EMC_ODT_WRITE */
-			0x00000000, /* EMC_ODT_READ */
-			0x00005088, /* EMC_FBIO_CFG5 */
-			0xf0040191, /* EMC_CFG_DIG_DLL */
-			0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
-			0x00000008, /* EMC_DLL_XFORM_DQS4 */
-			0x00000008, /* EMC_DLL_XFORM_DQS5 */
-			0x00000008, /* EMC_DLL_XFORM_DQS6 */
-			0x00000008, /* EMC_DLL_XFORM_DQS7 */
-			0x00018007, /* EMC_DLL_XFORM_QUSE4 */
-			0x00018007, /* EMC_DLL_XFORM_QUSE5 */
-			0x00018007, /* EMC_DLL_XFORM_QUSE6 */
-			0x00018007, /* EMC_DLL_XFORM_QUSE7 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
-			0x001112a0, /* EMC_XM2CMDPADCTRL */
-			0x00000000, /* EMC_XM2CMDPADCTRL4 */
-			0x0000013d, /* EMC_XM2DQSPADCTRL2 */
-			0x00000000, /* EMC_XM2DQPADCTRL2 */
-			0x77ffc085, /* EMC_XM2CLKPADCTRL */
-			0x81f1f508, /* EMC_XM2COMPPADCTRL */
-			0x07077504, /* EMC_XM2VTTGENPADCTRL */
-			0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
-			0x0000003f, /* EMC_DSR_VTTGEN_DRV */
-			0x00000000, /* EMC_TXDSRVTTGEN */
-			0x02000000, /* EMC_FBIO_SPARE */
-			0x00000802, /* EMC_CTT_TERM_CTRL */
-			0x00020000, /* EMC_ZCAL_INTERVAL */
-			0x00000120, /* EMC_ZCAL_WAIT_CNT */
-			0x00d5000f, /* EMC_MRS_WAIT_CNT */
-			0x00d5000f, /* EMC_MRS_WAIT_CNT2 */
-			0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-			0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-			0x00000000, /* EMC_CTT */
-			0x00000000, /* EMC_CTT_DURATION */
-			0x8000368a, /* EMC_DYN_SELF_REF_CONTROL */
-			0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
-			0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
-			0x0800000d, /* MC_EMEM_ARB_CFG */
-			0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */
-			0x00000005, /* MC_EMEM_ARB_TIMING_RCD */
-			0x00000006, /* MC_EMEM_ARB_TIMING_RP */
-			0x00000015, /* MC_EMEM_ARB_TIMING_RC */
-			0x0000000e, /* MC_EMEM_ARB_TIMING_RAS */
-			0x00000012, /* MC_EMEM_ARB_TIMING_FAW */
-			0x00000002, /* MC_EMEM_ARB_TIMING_RRD */
-			0x00000004, /* MC_EMEM_ARB_TIMING_RAP2PRE */
-			0x0000000e, /* MC_EMEM_ARB_TIMING_WAP2PRE */
-			0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
-			0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
-			0x00000006, /* MC_EMEM_ARB_TIMING_R2W */
-			0x00000009, /* MC_EMEM_ARB_TIMING_W2R */
-			0x09060202, /* MC_EMEM_ARB_DA_TURNS */
-			0x001a1015, /* MC_EMEM_ARB_DA_COVERS */
-			0x734e2916, /* MC_EMEM_ARB_MISC0 */
-			0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
-		},
-		{
-			0x00000000, /* EMC_CDB_CNTL_1 */
-			0x00000006, /* EMC_FBIO_CFG6 */
-			0x0000000c, /* EMC_QUSE */
-			0x0000000a, /* EMC_EINPUT */
-			0x00000006, /* EMC_EINPUT_DURATION */
-			0x00000008, /* EMC_DLL_XFORM_DQS0 */
-			0x0000000d, /* EMC_QSAFE */
-			0x00018007, /* EMC_DLL_XFORM_QUSE0 */
-			0x00000015, /* EMC_RDV */
-			0x00249249, /* EMC_XM2DQSPADCTRL4 */
-			0x20820800, /* EMC_XM2DQSPADCTRL3 */
-			0x00008008, /* EMC_DLL_XFORM_DQ0 */
-			0xa0f10202, /* EMC_AUTO_CAL_CONFIG */
-			0x00000000, /* EMC_DLL_XFORM_ADDR0 */
-			0x00000a0a, /* EMC_XM2CLKPADCTRL2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR1 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR2 */
-			0x00000008, /* EMC_DLL_XFORM_DQS1 */
-			0x00000008, /* EMC_DLL_XFORM_DQS2 */
-			0x00000008, /* EMC_DLL_XFORM_DQS3 */
-			0x00000008, /* EMC_DLL_XFORM_DQ1 */
-			0x00008008, /* EMC_DLL_XFORM_DQ2 */
-			0x00008008, /* EMC_DLL_XFORM_DQ3 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
-			0x00018007, /* EMC_DLL_XFORM_QUSE1 */
-			0x00018007, /* EMC_DLL_XFORM_QUSE2 */
-			0x00018007, /* EMC_DLL_XFORM_QUSE3 */
-		},
-		{
-			0x00000000, /* EMC_CDB_CNTL_1 */
-			0x00000006, /* EMC_FBIO_CFG6 */
-			0x0000000c, /* EMC_QUSE */
-			0x0000000a, /* EMC_EINPUT */
-			0x00000006, /* EMC_EINPUT_DURATION */
-			0x00000008, /* EMC_DLL_XFORM_DQS0 */
-			0x0000000d, /* EMC_QSAFE */
-			0x00018007, /* EMC_DLL_XFORM_QUSE0 */
-			0x00000015, /* EMC_RDV */
-			0x00249249, /* EMC_XM2DQSPADCTRL4 */
-			0x20820800, /* EMC_XM2DQSPADCTRL3 */
-			0x00008008, /* EMC_DLL_XFORM_DQ0 */
-			0xa8f10f0f, /* EMC_AUTO_CAL_CONFIG */
-			0x00000000, /* EMC_DLL_XFORM_ADDR0 */
-			0x00000a0a, /* EMC_XM2CLKPADCTRL2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR1 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR2 */
-			0x00000008, /* EMC_DLL_XFORM_DQS1 */
-			0x00000008, /* EMC_DLL_XFORM_DQS2 */
-			0x00000008, /* EMC_DLL_XFORM_DQS3 */
-			0x00000008, /* EMC_DLL_XFORM_DQ1 */
-			0x00008008, /* EMC_DLL_XFORM_DQ2 */
-			0x00008008, /* EMC_DLL_XFORM_DQ3 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
-			0x00018007, /* EMC_DLL_XFORM_QUSE1 */
-			0x00018007, /* EMC_DLL_XFORM_QUSE2 */
-			0x00018007, /* EMC_DLL_XFORM_QUSE3 */
-		},
-		{
-			0x000001cd, /* MC_PTSA_GRANT_DECREMENT */
-			0x00080008, /* MC_LATENCY_ALLOWANCE_G2_0 */
-			0x00080008, /* MC_LATENCY_ALLOWANCE_G2_1 */
-			0x0009000a, /* MC_LATENCY_ALLOWANCE_NV_0 */
-			0x0000000a, /* MC_LATENCY_ALLOWANCE_NV2_0 */
-			0x000a000a, /* MC_LATENCY_ALLOWANCE_NV_2 */
-			0x000e000a, /* MC_LATENCY_ALLOWANCE_NV_1 */
-			0x0000000e, /* MC_LATENCY_ALLOWANCE_NV2_1 */
-			0x000e000e, /* MC_LATENCY_ALLOWANCE_NV3 */
-			0x0060002d, /* MC_LATENCY_ALLOWANCE_EPP_0 */
-			0x00600060, /* MC_LATENCY_ALLOWANCE_EPP_1 */
-		},
-		0x0000004b, /* EMC_ZCAL_WAIT_CNT after clock change */
-		0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
-		0x53000000, /* EMC_CFG */
-		0x80000f15, /* Mode Register 0 */
-		0x80100002, /* Mode Register 1 */
-		0x80200420, /* Mode Register 2 */
-		0x00000000, /* Mode Register 4 */
-		1200,       /* expected dvfs latency (ns) */
-	},
-};
-
-
-static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
+static struct tegra11_emc_table h5tc4g63afr_pba_table[] = {
 	{
 		0x41,       /* Rev 4.0.3 */
 		12750,      /* SDRAM frequency */
@@ -5131,28 +2578,15 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
 	},
 };
 
-static struct tegra11_emc_pdata p2454_h5tc4g63afr_pba_pdata = {
-	.description = "p2454_h5tc4g63afr_pba",
-	.tables = p2454_h5tc4g63afr_pba_table,
-	.num_tables = ARRAY_SIZE(p2454_h5tc4g63afr_pba_table),
-};
-
-static struct tegra11_emc_pdata p2560_h5tc4g63afr_pba_pdata = {
-	.description = "p2560_h5tc4g63afr_pba",
-	.tables = p2560_h5tc4g63afr_pba_table,
-	.num_tables = ARRAY_SIZE(p2560_h5tc4g63afr_pba_table),
+static struct tegra11_emc_pdata h5tc4g63afr_pba_pdata = {
+	.description = "h5tc4g63afr_pba",
+	.tables = h5tc4g63afr_pba_table,
+	.num_tables = ARRAY_SIZE(h5tc4g63afr_pba_table),
 };
 
 static struct tegra11_emc_pdata *roth_get_emc_data(void)
 {
-	struct board_info board_info;
-
-	tegra_get_board_info(&board_info);
-
-	if (board_info.board_id == BOARD_P2560)
-		return &p2560_h5tc4g63afr_pba_pdata;
-	else
-		return &p2454_h5tc4g63afr_pba_pdata;
+	return &h5tc4g63afr_pba_pdata;
 }
 
 int __init roth_emc_init(void)
diff --git a/arch/arm/mach-tegra/board-roth-panel.c b/arch/arm/mach-tegra/board-roth-panel.c
index ac67ca16f1dc..94ee9e3317c6 100644
--- a/arch/arm/mach-tegra/board-roth-panel.c
+++ b/arch/arm/mach-tegra/board-roth-panel.c
@@ -319,7 +319,7 @@ static u8 panel_disp_ctrl1[] = {0xb5, 0x34, 0x20, 0x40, 0x0, 0x20};
 static u8 panel_disp_ctrl2[] = {0xb6, 0x04, 0x74, 0x0f, 0x16, 0x13};
 static u8 panel_internal_clk[] = {0xc0, 0x01, 0x08};
 static u8 panel_pwr_ctrl3[] = {
-	0xc3, 0x0, 0x09, 0x10, 0x02, 0x0, 0x66, 0x20, 0x13, 0x0};
+	0xc3, 0x0, 0x09, 0x10, 0x02, 0x0, 0x66, 0x00, 0x13, 0x0};
 static u8 panel_pwr_ctrl4[] = {0xc4, 0x23, 0x24, 0x12, 0x12, 0x60};
 static u8 panel_positive_gamma_red[] = {
 	0xd0, 0x21, 0x25, 0x67, 0x36, 0x0a, 0x06, 0x61, 0x23, 0x03};
@@ -373,7 +373,7 @@ static struct tegra_dsi_cmd dsi_init_cmd[] = {
 	DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_positive_gamma_blue),
 	DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_negetive_gamma_blue),
 
-	DSI_CMD_SHORT(DSI_DCS_WRITE_1_PARAM, DSI_DCS_SET_ADDR_MODE, 0x08),
+	DSI_CMD_SHORT(DSI_DCS_WRITE_1_PARAM, DSI_DCS_SET_ADDR_MODE, 0x0B),
 
 	/* panel OTP 2 */
 	DSI_CMD_SHORT(DSI_GENERIC_SHORT_WRITE_2_PARAMS, 0xf9, 0x0),
@@ -624,11 +624,11 @@ static struct tegra_dc_mode roth_dsi_modes[] = {
 		.h_sync_width = 4,
 		.v_sync_width = 4,
 		.h_back_porch = 112,
-		.v_back_porch = 7,
+		.v_back_porch = 12,
 		.h_active = 720,
 		.v_active = 1280,
 		.h_front_porch = 12,
-		.v_front_porch = 20,
+		.v_front_porch = 8,
 	},
 };
 
diff --git a/arch/arm/mach-tegra/board-roth-power.c b/arch/arm/mach-tegra/board-roth-power.c
index 0a658a5c9a87..f02a7bb51f98 100644
--- a/arch/arm/mach-tegra/board-roth-power.c
+++ b/arch/arm/mach-tegra/board-roth-power.c
@@ -28,6 +28,7 @@
 #include <linux/mfd/palmas.h>
 #include <linux/regulator/tps51632-regulator.h>
 #include <linux/power/bq2419x-charger.h>
+#include <linux/max17048_battery.h>
 #include <linux/gpio.h>
 #include <linux/regulator/userspace-consumer.h>
 
@@ -130,6 +131,43 @@ static struct i2c_board_info __initdata bq2419x_boardinfo[] = {
 	},
 };
 
+struct max17048_battery_model max17048_mdata __initdata = {
+	.rcomp          = 105,
+	.soccheck_A     = 240,
+	.soccheck_B     = 242,
+	.bits           = 19,
+	.alert_threshold = 0x00,
+	.one_percent_alerts = 0x40,
+	.alert_on_reset = 0x40,
+	.rcomp_seg      = 0x0080,
+	.hibernate      = 0x3080,
+	.vreset         = 0x3c96,
+	.valert         = 0xD4AA,
+	.ocvtest        = 55728,
+	.data_tbl = {
+		0xA9, 0x90, 0xB1, 0x60, 0xB5, 0xC0, 0xB7, 0x80,
+		0xBA, 0xF0, 0xBB, 0xA0, 0xBB, 0xE0, 0xBC, 0x50,
+		0xBC, 0xC0, 0xBD, 0x30, 0xBE, 0xD0, 0xC0, 0x90,
+		0xC1, 0xD0, 0xC6, 0x70, 0xCA, 0xD0, 0xCF, 0xB0,
+		0x0A, 0xF0, 0x0D, 0xE0, 0x0B, 0x30, 0x01, 0x90,
+		0x53, 0xB0, 0x78, 0xD0, 0x77, 0xB0, 0x7C, 0xF0,
+		0x7A, 0x70, 0x13, 0xE0, 0x13, 0x90, 0x1F, 0x30,
+		0x19, 0x00, 0x12, 0x10, 0x10, 0xB0, 0x10, 0xB0,
+	},
+};
+
+struct max17048_platform_data max17048_pdata = {
+	.model_data = &max17048_mdata,
+};
+
+static struct i2c_board_info __initdata max17048_boardinfo[] = {
+	{
+		I2C_BOARD_INFO("max17048", 0x36),
+		.platform_data  = &max17048_pdata,
+	},
+};
+
+
 /************************ Palmas based regulator ****************/
 static struct regulator_consumer_supply palmas_smps12_supply[] = {
 	REGULATOR_SUPPLY("vddio_ddr0", NULL),
@@ -158,7 +196,6 @@ static struct regulator_consumer_supply palmas_smps3_supply[] = {
 	REGULATOR_SUPPLY("pwrdet_bb", NULL),
 	REGULATOR_SUPPLY("pwrdet_cam", NULL),
 	REGULATOR_SUPPLY("dbvdd", NULL),
-	REGULATOR_SUPPLY("dvdd_lcd", NULL),
 	REGULATOR_SUPPLY("vlogic", "0-0068"),
 };
 
@@ -180,8 +217,6 @@ static struct regulator_consumer_supply palmas_smps8_supply[] = {
 	REGULATOR_SUPPLY("avdd_csi_dsi_pll", "vi"),
 	REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.2"),
 	REGULATOR_SUPPLY("avddio_usb", "tegra-ehci.2"),
-	/* This is an optional assignment, keep it as the last entry*/
-	REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
 };
 
 static struct regulator_consumer_supply palmas_smps9_supply[] = {
@@ -205,6 +240,10 @@ static struct regulator_consumer_supply palmas_ldo3_supply[] = {
 	REGULATOR_SUPPLY("pwrdet_mipi", NULL),
 };
 
+static struct regulator_consumer_supply palmas_ldo4_supply[] = {
+        REGULATOR_SUPPLY("vpp_fuse", NULL),
+};
+
 static struct regulator_consumer_supply palmas_ldo5_supply[] = {
 	REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
 };
@@ -256,6 +295,7 @@ PALMAS_PDATA_INIT(smps9, 2800,  2800, NULL, 0, 0, 0, NORMAL);
 PALMAS_PDATA_INIT(smps10, 5000,  5000, NULL, 0, 0, 0, 0);
 PALMAS_PDATA_INIT(ldo2, 2800,  2800, NULL, 0, 0, 1, 0);
 PALMAS_PDATA_INIT(ldo3, 1200,  1200, NULL, 1, 1, 1, 0);
+PALMAS_PDATA_INIT(ldo4, 1800,  1800, NULL, 0, 0, 1, 0);
 PALMAS_PDATA_INIT(ldo5, 1200,  1200, NULL, 0, 0, 1, 0);
 PALMAS_PDATA_INIT(ldo6, 2850,  2850, NULL, 0, 0, 1, 0);
 PALMAS_PDATA_INIT(ldo8, 900,  900, NULL, 1, 1, 1, 0);
@@ -279,8 +319,8 @@ static struct regulator_init_data *roth_reg_data[PALMAS_NUM_REGS] = {
 	NULL,	/* LDO1 */
 	PALMAS_REG_PDATA(ldo2),
 	PALMAS_REG_PDATA(ldo3),
-	NULL,
-	NULL,
+	PALMAS_REG_PDATA(ldo4),
+	PALMAS_REG_PDATA(ldo5),
 	PALMAS_REG_PDATA(ldo6),
 	NULL,
 	PALMAS_REG_PDATA(ldo8),
@@ -451,6 +491,10 @@ static struct regulator_consumer_supply fixed_reg_dvdd_ts_supply[] = {
 	REGULATOR_SUPPLY("dvdd", "spi3.2"),
 };
 
+/* EN_1V8_TS From TEGRA_GPIO_PU4 */
+static struct regulator_consumer_supply fixed_reg_dvdd_lcd_supply[] = {
+	REGULATOR_SUPPLY("dvdd_lcd", NULL),
+};
 /* Macro for defining fixed regulator sub device data */
 #define FIXED_SUPPLY(_name) "fixed_reg_"#_name
 #define FIXED_REG(_id, _var, _name, _in_supply, _always_on, _boot_on,	\
@@ -521,6 +565,10 @@ FIXED_REG(7,	com_1v8,	com_1v8,
 	palmas_rails(smps3),	0,	0,
 	TEGRA_GPIO_PX1,	false,	true,	0,	1800);
 
+FIXED_REG(8,	dvdd_lcd,	dvdd_lcd,
+	palmas_rails(smps3),	0,	0,
+	TEGRA_GPIO_PU4,	false,	true,	1,	1800);
+
 /*
  * Creating the fixed regulator device tables
  */
@@ -550,21 +598,14 @@ static struct platform_device *fixed_reg_devs_roth[] = {
 	ADD_FIXED_REG(com_3v3),
 	ADD_FIXED_REG(sd_3v3),
 	ADD_FIXED_REG(com_1v8),
+	ADD_FIXED_REG(dvdd_lcd),
 };
 
 int __init roth_palmas_regulator_init(void)
 {
 	void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
-	struct board_info board_info;
 	u32 pmc_ctrl;
 	int i;
-	int new_brd = 0;
-
-	tegra_get_board_info(&board_info);
-	new_brd = (board_info.board_id == BOARD_P2560);
-	/* Let avdd_hdmi_pll not depend on smps8 for roth 2560 */
-	if (new_brd)
-		(*PALMAS_REG_PDATA(smps8)).num_consumer_supplies--;
 
 	/* TPS65913: Normal state of INT request line is LOW.
 	 * configure the power management controller to trigger PMU
@@ -579,11 +620,7 @@ int __init roth_palmas_regulator_init(void)
 			PALMAS_REGULATOR_CONFIG_SUSPEND_TRACKING_DISABLE;
 
 	for (i = 0; i < PALMAS_NUM_REGS ; i++) {
-		/* Include ldo5 for roth 2560 */
-		if ((roth_reg_init[i] == PALMAS_REG_INIT_DATA(ldo5)) && new_brd)
-			pmic_platform.reg_data[i] = PALMAS_REG_PDATA(ldo5);
-		else
-			pmic_platform.reg_data[i] = roth_reg_data[i];
+		pmic_platform.reg_data[i] = roth_reg_data[i];
 		pmic_platform.reg_init[i] = roth_reg_init[i];
 	}
 
@@ -704,14 +741,13 @@ subsys_initcall_sync(roth_fixed_regulator_init);
 
 int __init roth_regulator_init(void)
 {
-	struct board_info board_info;
 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
 	roth_cl_dvfs_init();
 #endif
-	tegra_get_board_info(&board_info);
 	roth_palmas_regulator_init();
 
 	i2c_register_board_info(4, tps51632_boardinfo, 1);
+	i2c_register_board_info(0, max17048_boardinfo, 1);
 	i2c_register_board_info(0, bq2419x_boardinfo, 1);
 	platform_device_register(&roth_pda_power_device);
 	return 0;
diff --git a/arch/arm/mach-tegra/board-roth-sensors.c b/arch/arm/mach-tegra/board-roth-sensors.c
index 1f62e2086f9a..c0f4a1cbc2c6 100644
--- a/arch/arm/mach-tegra/board-roth-sensors.c
+++ b/arch/arm/mach-tegra/board-roth-sensors.c
@@ -488,8 +488,6 @@ int __init roth_sensors_init(void)
 {
 	int err;
 
-	tegra_get_board_info(&board_info);
-
 	err = roth_nct1008_init();
 	if (err)
 		return err;
@@ -498,9 +496,5 @@ int __init roth_sensors_init(void)
 
 	roth_fan_est_init();
 
-	if (0)
-		i2c_register_board_info(0, bq20z45_pdata,
-			ARRAY_SIZE(bq20z45_pdata));
-
 	return 0;
 }
diff --git a/arch/arm/mach-tegra/board-roth.c b/arch/arm/mach-tegra/board-roth.c
index 7d0d5755627f..69a4e2ca24e4 100644
--- a/arch/arm/mach-tegra/board-roth.c
+++ b/arch/arm/mach-tegra/board-roth.c
@@ -51,7 +51,7 @@
 #include <mach/clk.h>
 #include <mach/irqs.h>
 #include <mach/pinmux.h>
-#include <mach/pinmux-tegra30.h>
+#include <mach/pinmux-t11.h>
 #include <mach/io_dpd.h>
 #include <mach/i2s.h>
 #include <mach/isomgr.h>
@@ -247,19 +247,10 @@ static struct i2c_board_info __initdata roth_codec_tfa9887R_info = {
 static struct i2c_board_info __initdata roth_codec_tfa9887L_info = {
 	I2C_BOARD_INFO("tfa9887L", 0x34),
 };
-
-/* On A01, Left Speaker is moved to 0x34 */
-static struct i2c_board_info __initdata roth_codec_tfa9887L_info_a01 = {
-	I2C_BOARD_INFO("tfa9887L", 0x34),
-};
 #endif
 
 static void roth_i2c_init(void)
 {
-	struct board_info board_info;
-
-	tegra_get_board_info(&board_info);
-
 	tegra11_i2c_device1.dev.platform_data = &roth_i2c1_platform_data;
 	tegra11_i2c_device2.dev.platform_data = &roth_i2c2_platform_data;
 	tegra11_i2c_device3.dev.platform_data = &roth_i2c3_platform_data;
@@ -274,11 +265,7 @@ static void roth_i2c_init(void)
 
 	i2c_register_board_info(0, &rt5640_board_info, 1);
 	i2c_register_board_info(0, &roth_codec_tfa9887R_info, 1);
-
-	if (board_info.fab >= BOARD_FAB_A01)
-		i2c_register_board_info(0, &roth_codec_tfa9887L_info_a01, 1);
-	else
-		i2c_register_board_info(0, &roth_codec_tfa9887L_info, 1);
+	i2c_register_board_info(0, &roth_codec_tfa9887L_info, 1);
 }
 
 static struct platform_device *roth_uart_devices[] __initdata = {
@@ -450,7 +437,6 @@ static struct platform_device *roth_devices[] __initdata = {
 	&tegra_aes_device,
 #endif
 
-	&tegra_pwfm_device,
 	&roth_leds_pwm_device,
 };
 
@@ -554,10 +540,6 @@ static void roth_usb_init(void) { }
 
 static void roth_audio_init(void)
 {
-	struct board_info board_info;
-
-	tegra_get_board_info(&board_info);
-
 	roth_audio_pdata.codec_name = "rt5640.0-001c";
 	roth_audio_pdata.codec_dai_name = "rt5640-aif1";
 }
@@ -643,30 +625,27 @@ static int __init roth_touch_init(void)
 	struct board_info board_info;
 
 	tegra_get_board_info(&board_info);
-	if (board_info.board_id == BOARD_P2560) {
-		int touch_panel_id = tegra_get_touch_panel_id();
-		if (touch_panel_id == PANEL_TPK ||
-				touch_panel_id == PANEL_WINTEK) {
-			int err;
-			err = gpio_request(TOUCH_GPIO_CLK, "touch-gpio-clk");
+	int touch_panel_id = tegra_get_touch_panel_id();
+	if (touch_panel_id == PANEL_TPK ||
+			touch_panel_id == PANEL_WINTEK) {
+		int err;
+		err = gpio_request(TOUCH_GPIO_CLK, "touch-gpio-clk");
+		if (err < 0)
+			pr_err("%s: gpio_request failed %d\n",
+				__func__, err);
+		else {
+			err = gpio_direction_output(TOUCH_GPIO_CLK, 0);
 			if (err < 0)
-				pr_err("%s: gpio_request failed %d\n",
-					__func__, err);
-			else {
-				err = gpio_direction_output(TOUCH_GPIO_CLK, 0);
-				if (err < 0)
-					pr_err("%s: set output failed %d\n",
-					__func__, err);
-				gpio_free(TOUCH_GPIO_CLK);
-			}
-			tegra_pinmux_set_pullupdown(TOUCH_GPIO_CLK_PG,
-							TEGRA_PUPD_NORMAL);
-			tegra_pinmux_set_tristate(TOUCH_GPIO_CLK_PG,
-							TEGRA_TRI_TRISTATE);
-			rm31080ts_roth_data.name_of_clock = NULL;
-			rm31080ts_roth_data.name_of_clock_con = NULL;
-		} else
-			tegra_clk_init_from_table(touch_clk_init_table);
+				pr_err("%s: set output failed %d\n",
+				__func__, err);
+			gpio_free(TOUCH_GPIO_CLK);
+		}
+		tegra_pinmux_set_pullupdown(TOUCH_GPIO_CLK_PG,
+						TEGRA_PUPD_NORMAL);
+		tegra_pinmux_set_tristate(TOUCH_GPIO_CLK_PG,
+						TEGRA_TRI_TRISTATE);
+		rm31080ts_roth_data.name_of_clock = NULL;
+		rm31080ts_roth_data.name_of_clock_con = NULL;
 	} else
 		tegra_clk_init_from_table(touch_clk_init_table);
 	rm31080a_roth_spi_board[0].irq =
@@ -679,18 +658,6 @@ static int __init roth_touch_init(void)
 	return 0;
 }
 
-static int __init roth_revision_init(void)
-{
-	struct board_info board_info;
-	tegra_get_board_info(&board_info);
-	system_rev = 0;
-	if (board_info.board_id == BOARD_P2454)
-		system_rev = P2454;
-	else
-		system_rev = P2560;
-	return 0;
-}
-
 static void __init tegra_roth_init(void)
 {
 	tegra_clk_init_from_table(roth_clk_init_table);
@@ -732,7 +699,6 @@ static void __init tegra_roth_init(void)
 	roth_soctherm_init();
 	roth_fan_init();
 	tegra_register_fuse();
-	roth_revision_init();
 }
 
 static void __init roth_ramconsole_reserve(unsigned long size)