diff options
| author | WayneWWW <WayneWWW@devtalk.nvidia.com> | 2017-12-10 09:42:48 +0900 |
|---|---|---|
| committer | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2017-06-30 18:24:08 +0200 |
| commit | e5ea4ac452f04e3d534567928b39afef7d11b94c (patch) | |
| tree | a4699a0a76b50f02a3f0c230be48829a0ce88566 | |
| parent | 0fd52954473907e506f0a30c9ce69b2f83286ff7 (diff) | |
video: tegra: sor: set drive current for lane4
Drive current for LANE4 was not set if configured as 24bpp LVDS out.
Fix it by programming proper drive current register if using 24bpp out.
https://devtalk.nvidia.com/default/topic/1003030
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Dominik Sliwa <dominik.sliwa@toradex.com>
| -rw-r--r-- | drivers/video/tegra/dc/sor.c | 4 | ||||
| -rw-r--r-- | drivers/video/tegra/dc/sor_regs.h | 1 |
2 files changed, 5 insertions, 0 deletions
diff --git a/drivers/video/tegra/dc/sor.c b/drivers/video/tegra/dc/sor.c index 43f7cb0cc8a4..ee75338e4037 100644 --- a/drivers/video/tegra/dc/sor.c +++ b/drivers/video/tegra/dc/sor.c @@ -186,6 +186,7 @@ static int dbg_sor_show(struct seq_file *s, void *unused) DUMP_REG(NV_SOR_DC(0)); DUMP_REG(NV_SOR_DC(1)); DUMP_REG(NV_SOR_LANE_DRIVE_CURRENT(0)); + DUMP_REG(NV_SOR_LANE4_DRIVE_CURRENT(0)); DUMP_REG(NV_SOR_PR(0)); DUMP_REG(NV_SOR_LANE4_PREEMPHASIS(0)); DUMP_REG(NV_SOR_POSTCURSOR(0)); @@ -1257,6 +1258,9 @@ void tegra_dc_sor_enable_lvds(struct tegra_dc_sor_data *sor, tegra_sor_writel(sor, NV_SOR_LVDS, reg_val); tegra_sor_writel(sor, NV_SOR_LANE_DRIVE_CURRENT(sor->portnum), 0x40404040); + if (!conforming && (sor->dc->pdata->default_out->depth == 24)) + tegra_sor_writel(sor, NV_SOR_LANE4_DRIVE_CURRENT(sor->portnum), + 0x40); #if 0 tegra_sor_write_field(sor, NV_SOR_LVDS, diff --git a/drivers/video/tegra/dc/sor_regs.h b/drivers/video/tegra/dc/sor_regs.h index cbf4b94c1664..8e1cc1c3231c 100644 --- a/drivers/video/tegra/dc/sor_regs.h +++ b/drivers/video/tegra/dc/sor_regs.h @@ -611,6 +611,7 @@ #define NV_SOR_DC_LANE0_DP_LANE2_P1_LEVEL2 (43) #define NV_SOR_DC_LANE0_DP_LANE2_P0_LEVEL3 (51) #define NV_SOR_LANE_DRIVE_CURRENT(i) (0x4e + (i)) +#define NV_SOR_LANE4_DRIVE_CURRENT(i) (0x50 + (i)) #define NV_SOR_PR(i) (0x52 + (i)) #define NV_SOR_PR_LANE3_DP_LANE3_SHIFT (24) #define NV_SOR_PR_LANE3_DP_LANE3_MASK (0xff << 24) |