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authorPeter Horton <zero@colonel-panic.org>2008-03-25 12:39:09 +0100
committerJeff Garzik <jgarzik@redhat.com>2008-04-16 20:40:01 -0400
commit10c6462090cccb643f31e26a14cb933bc31d8666 (patch)
tree9e5c5c509d86d5ab425a089bd95652d46aeac73c
parent48dd59e398455b58910910bc272e0da85f11bd98 (diff)
[netdrvr] tulip: Better MWI workaround for 21143 rev 65 chip errata
This patch works around the MWI bug on the DC21143 rev 65 Tulip by ensuring that the receive buffers don't end on a cache line boundary (as documented in the errata). This patch is required for the MIPS based Cobalt Qube/RaQ as supporting the extra PCI commands seems to reduce the chance of a hard lockup between the Tulip and the PCI bridge. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
-rw-r--r--drivers/net/tulip/tulip.h7
-rw-r--r--drivers/net/tulip/tulip_core.c19
2 files changed, 11 insertions, 15 deletions
diff --git a/drivers/net/tulip/tulip.h b/drivers/net/tulip/tulip.h
index 3f69f53d7768..908422f2f320 100644
--- a/drivers/net/tulip/tulip.h
+++ b/drivers/net/tulip/tulip.h
@@ -268,7 +268,12 @@ enum t21143_csr6_bits {
#define RX_RING_SIZE 128
#define MEDIA_MASK 31
-#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer. */
+/* The receiver on the DC21143 rev 65 can fail to close the last
+ * receive descriptor in certain circumstances (see errata) when
+ * using MWI. This can only occur if the receive buffer ends on
+ * a cache line boundary, so the "+ 4" below ensures it doesn't.
+ */
+#define PKT_BUF_SZ (1536 + 4) /* Size of each temporary Rx buffer. */
#define TULIP_MIN_CACHE_LINE 8 /* in units of 32-bit words */
diff --git a/drivers/net/tulip/tulip_core.c b/drivers/net/tulip/tulip_core.c
index 82f404b76d81..fa1c1c329a2d 100644
--- a/drivers/net/tulip/tulip_core.c
+++ b/drivers/net/tulip/tulip_core.c
@@ -1154,18 +1154,13 @@ static void __devinit tulip_mwi_config (struct pci_dev *pdev,
tp->csr0 = csr0 = 0;
- /* if we have any cache line size at all, we can do MRM */
- csr0 |= MRM;
+ /* if we have any cache line size at all, we can do MRM and MWI */
+ csr0 |= MRM | MWI;
- /* ...and barring hardware bugs, MWI */
- if (!(tp->chip_id == DC21143 && tp->revision == 65))
- csr0 |= MWI;
-
- /* set or disable MWI in the standard PCI command bit.
- * Check for the case where mwi is desired but not available
+ /* Enable MWI in the standard PCI command bit.
+ * Check for the case where MWI is desired but not available
*/
- if (csr0 & MWI) pci_try_set_mwi(pdev);
- else pci_clear_mwi(pdev);
+ pci_try_set_mwi(pdev);
/* read result from hardware (in case bit refused to enable) */
pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
@@ -1401,10 +1396,6 @@ static int __devinit tulip_init_one (struct pci_dev *pdev,
#ifdef CONFIG_TULIP_MWI
if (!force_csr0 && (tp->flags & HAS_PCI_MWI))
tulip_mwi_config (pdev, dev);
-#else
- /* MWI is broken for DC21143 rev 65... */
- if (chip_idx == DC21143 && pdev->revision == 65)
- tp->csr0 &= ~MWI;
#endif
/* Stop the chip's Tx and Rx processes. */